ak4566vn AKM Semiconductor, Inc., ak4566vn Datasheet
ak4566vn
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ASAHI KASEI 20bit Stereo CODEC with built-in IPGA & HP-AMP The AK4566 is a 20bit CODEC with built-in Input PGA and Headphone Amplifier. The AK4566 includes microphone/line input selector and ALC circuit for input, and Mono line output buffer, analog ...
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ASAHI KASEI AVDD VREF VREF VCOM VCOM AINL1 AINL2 IPGA AINR1 AINR2 HP-amp HPL HP-Amp HPR MOUT MOUT LIN RIN MIN HVDD HVSS MUTET AVSS REV 0.5 AKM CONFIDENTIAL DVDD IPGA & ADC ADC HPF DAC BOOST DATT DAC DVSS ...
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... ASAHI KASEI n Ordering Guide AK4566VN -40 AKD4566 Evaluation board for AK4566 n Pin Layout PDN 1 CSN 2 CCLK 3 CDTI 4 LRCK 5 MCLK 6 BICK 7 REV 0.5 AKM CONFIDENTIAL +85 C 28pin QFN (0.5mm pitch Top View [AK4566] VREF LIN RIN MIN MOUT MUTET HPL ...
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ASAHI KASEI No. Pin Name I/O Power-down Pin 1 PDN I When at “L”, the AK4566 is in power-down mode and is held in reset. The AK4566 should always be reset upon power-up. 2 CSN I Control Data Chip Select ...
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ASAHI KASEI (AVSS, DVSS, HVSS=0V; Note 1) Parameter Power Supplies Analog Digital HP-AMP |AVSS – HVSS| |AVSS – DVSS| Input Current (any pins except for supplies) Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Note 1. All voltages ...
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ASAHI KASEI (Ta=25 C; AVDD=DVDD=HVDD=3.0V, AVSS =DVSS=HVSS=0V; fs=44.1kHz; BOOST OFF; Signal Frequency =1kHz; Measurement band width=20Hz 20kHz; unless otherwise specified) Parameter ADC Resolution IPGA Characteristics: (AINL1, AINR1 pins) (LINE IN) Input Voltage Input Resistance Step Size Gain Control Range IPGA ...
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ASAHI KASEI Parameter Analog Input: (LIN/RIN/MIN pins) Input Resistance Gain LIN/RIN MOUT MIN MOUT, LIN/MIN HPL, RIN/MIN HPR Power Supplies Power Supply Current Normal Operation (PDN= “H”) AVDD + DVDD + HVDD Power-Down Mode (PDN= “L”) AVDD + DVDD + ...
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ASAHI KASEI (Ta=25 C; AVDD, DVDD, HVDD=2.5 Parameter ADC Digital Filter (LPF): Passband (Note 15) -1.0dB -3.0dB Stopband (Note 15) Passband Ripple Stopband Attenuation Group Delay (Note 16) Group Delay Distortion ADC Digital Filter (HPF): Frequency Response (Note 15) -3dB ...
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ASAHI KASEI 0 -5 -10 -15 -20 MIN -25 0.01 (Ta=25 C; AVDD, DVDD, HVDD = 2.5 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Voltage at AC Coupling (Note 19) High-Level Output Voltage (Iout = -100 A) Low-Level ...
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ASAHI KASEI (Ta=25 C; AVDD, DVDD, HVDD = 2.5 Parameter Master Clock Timing Frequency Pulse Width Low (Note 20) Pulse Width High (Note 20) AC Pulse Width (Note 21) LRCK Timing Frequency Duty Cycle Serial Interface Timing (Note 22) BICK ...
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ASAHI KASEI n Timing Diagram 1000pF MCLK Input MCLK tCLKH LRCK BICK tBCKH REV 0.5 AKM CONFIDENTIAL Measurement Point 100k AVSS AVSS Figure 4. MCLK AC Coupling Timing 1/fCLK tCLKL 1/fs tBCK tBCKL Figure 5. Clock Timing - 11 - ...
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ASAHI KASEI LRCK tBLR BICK tLRS SDTO SDTI CSN tCSS CCLK CDTI CSN CCLK CDTI D3 REV 0.5 AKM CONFIDENTIAL tLRB tSDS tSDH Figure 6. Serial Interface Timing tCCKL tCCKH tCDS tCDH C1 C0 R/W Figure 7. WRITE Command Input ...
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ASAHI KASEI CSN SDTO PDN REV 0.5 AKM CONFIDENTIAL tPDV tPD Figure 9. Power-down & Reset Timing - 13 - [AK4566] VIH VIL 50%DVDD VIL 2002/2 ...
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ASAHI KASEI n System Clock The external clocks required to operate the AK4566 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The frequency of ...
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ASAHI KASEI n Serial Data Interface The AK4566 interfaces with external system by using BICK, LRCK, SDTO and SDTI pins. Four data formats are available and are selected by setting DIF1 and DIF0 bits (Table 3). Mode 0 of SDTI ...
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ASAHI KASEI LRCK BICK(64fs) SDTO( SDTI( 16bit SDTI( 18bit SDTI( 20bit Lch Data LRCK ...
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ASAHI KASEI n ALC Operation [1] ALC Limiter Operation During the ALC limiter operation, when either output level of Lch or Rch in IPGA exceeds ALC limiter detection level set by LMTH bit, IPGA value is automatically attenuated by ALC ...
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ASAHI KASEI [3] ALC Operation Example The following registers should not be changed during the ALC operation: LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELMN. WR (Power Management Control & Signal Select) No Finish ALC mode and return to Manual ...
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ASAHI KASEI n IPGA Operation [Write Operation at ALC Enabled] The values of IPGA6-0 bits are ignored during ALC operation. [Write Operation at ALC Disabled] Channel independent zero crossing detection is used. If there is no zero crossings, then the ...
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ASAHI KASEI n Digital Attenuator The AK4566 has channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to -127dB or MUTE) of each channel (Table 19). At ...
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ASAHI KASEI n De-emphasis Filter The AK4566 includes a digital de-emphasis filter (tc = 50/ IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 16). n ...
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ASAHI KASEI n Power-Up/Down Sequence 1) ADC Power Supply (1) >150ns PDN pin (2) HPLMT, >0 HPRMT bit PMVCM bit Clock Input Don’t care PMADC bit (3) >0 ADC Internal PD(Power-down) State AIN pin (Hi-Z) SDTO pin Figure 17. Power-up/down ...
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ASAHI KASEI 2) DAC HP-amp Power supply voltage for headphone amp is supplied from HVDD pin and centered around VCOM. Load resistance of headphone output is min.20 . When PMHPL and PMHPR bit are “0”, headphone amplifiers are powered-down perfectly. ...
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ASAHI KASEI 3) DAC MOUT Power Supply (1) >150ns PDN pin (2) HPLMT, >0 HPRMT bit PMVCM bit Clock Input Don’t care PMDAC bit (3) >0 DAC Internal PD(Power-down) State SDTI pin PMMO bit ATTL/R7-0 bit 00H(MUTE) MMUTE, 10H(MUTE) ATTM3-0 ...
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ASAHI KASEI 4) LIN/RIN/MIN HP-amp, MOUT Power Supply (1) >150ns PDN pin (2) >0 PMVCM bit PMHPL/R bit, PMMO bit HPLMT, HPRMT bit LIN/RIN/MIN pin (Hi-Z) HPL/R pin MMUTE, 10H(MUTE) ATTM3-0 bit (Hi-Z) MOUT pin Figure 20. Power-up/down sequence of ...
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ASAHI KASEI n Serial Control Interface Internal registers may be written to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of Chip address (2bits, Fixed to “10”), Read/Write (1bit, Fixed to “1”, ...
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ASAHI KASEI n Register Map Addr Register Name 00H Power Management HPRMT 01H Input Select 02H Timer Select 03H ALC Mode Control 1 04H ALC Mode Control 2 05H IPGA Control 06H Mode Control MCKAC 07H DAC Control 08H Output ...
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ASAHI KASEI n Register Definitions Addr Register Name 00H Power Management HPRMT Default PMVCM: Power Management for VCOM Block 0: Power OFF (Default) 1: Power ON PMADC: Power Management for IPGA and ADC Blocks 0: Power OFF (Default) 1: Power ...
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ASAHI KASEI Addr Register Name 01H Input Select Default INL2-1: Select ON/OFF of IPGA Lch input. 0: OFF 1: ON Default: INL2=0, INL1=1 INR2-1: Select ON/OFF of IPGA Rch input. 0: OFF 1: ON Default: INR2=0, INR1=1 ADM: Mono Recording ...
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ASAHI KASEI Addr Register Name 02H Timer Select Default LTM1-0: ALC limiter operation period (Table 6) When zero crossing is disabled (ZELMN = “1”), the IPGA value is changed immediately by ALC limiter operation. When the IPGA value is changed ...
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ASAHI KASEI Addr Register Name 03H ALC Mode Control 1 Default LMTH: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 9) LMTH ALC Limiter Detection Level 0 ADC Input 6.0dBFS 1 ADC Input 4.0dBFS Table 9. ALC1 ...
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ASAHI KASEI Addr Register Name 04H ALC Mode Control 2 Default REF6-0: Reference Value at ALC Recovery Operation, 0.5dB step, 103 level, Default: “3FH” (Table 12) During the ALC recovery operation, if the IPGA value exceeds the set reference value ...
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ASAHI KASEI Addr Register Name 06H Mode Control MCKAC Default DFS: Sampling Speed Mode Select (Table 2) DIF1-0: Audio Data Interface Format Default: “10” (Mode 2) HPM: Mono Output Select of Headphone 0: Normal Operation (Default) 1: Mono. (L+R)/2 signal ...
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ASAHI KASEI Addr Register Name 07H DAC Control Default DEM1-0: De-emphasis Filter Frequency Select DEM1 Table 16. De-emphasis Filter Frequency Select BST1-0: Low Frequency Boost Function Select BST1 DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (Default) 1: Dependent ...
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ASAHI KASEI Addr Register Name 08H Output Select 0 Default DACL: DAC Lch output signal is added to Lch of headphone amp. 0: OFF (Default LINL: Input signal to LIN pin is added to Lch of headphone amp. ...
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ASAHI KASEI Addr Register Name 09H Output Select 1 Default DACM: DAC Lch and Rch outputs are added to MOUT buffer amp. Summation gain is -6dB for each channel. 0: OFF (Default LINM: Input signal to LIN pin ...
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ASAHI KASEI Addr Register Name 0AH DAC Lch ATT ATTL7 0BH DAC Rch ATT ATTR7 Default ATTL7-0: Setting of the attenuation value of output signal from DACL ATTR7-0: Setting of the attenuation value of output signal from DACR The AK4566 ...
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ASAHI KASEI Figure 24 shows the system connection diagram. An evaluation board [AKD4566] is available which demonstrates the optimum layout, power supply arrangements and measurement results µ DSP DIR Digital Ground Analog Ground ...
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ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4566 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10 ...
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ASAHI KASEI n Application Circuit Example AVDD VREF VREF VCOM VCOM IPGA & ADC AINL1 AINL2 IPGA AINR1 AINR2 HP-amp HPL HP-Amp HPR MOUT MOUT LIN RIN MIN HVDD HVSS MUTET AVSS REV 0.5 AKM CONFIDENTIAL DVDD AK4566 MCLK ADC ...
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ASAHI KASEI <Clock and Data Flow> 1) Analog Recording AVDD AK4566 VREF VREF VCOM VCOM IPGA & ADC AINL1 AINL2 IPGA ADC AINR1 AINR2 HP-amp HPL HP-Amp DAC HPR MOUT MOUT LIN RIN MIN HVDD HVSS MUTET AVSS Figure 26. ...
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ASAHI KASEI 2) Digital Recording AVDD AK4566 VREF VREF VCOM VCOM IPGA & ADC AINL1 AINL2 IPGA ADC AINR1 AINR2 HP-amp HPL HP-Amp DAC HPR MOUT MOUT LIN RIN MIN HVDD HVSS MUTET AVSS Figure 27. Clock and Data Flow ...
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ASAHI KASEI 3) Playback AVDD AK4566 VREF VREF VCOM VCOM IPGA & ADC AINL1 AINL2 IPGA ADC AINR1 AINR2 HP-amp HPL HP-Amp DAC HPR MOUT MOUT LIN RIN MIN HVDD HVSS MUTET AVSS Figure 28. Clock and Data Flow at ...
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ASAHI KASEI 28pin QFN (Unit: mm) 5.2 ± 0.20 5.0 ± 0. 0.22 ± 0.05 0.50 Note: The black parts of back package should be open. n Package & Lead frame material Package molding ...
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ASAHI KASEI These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...