ak4566vn AKM Semiconductor, Inc., ak4566vn Datasheet - Page 19

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ak4566vn

Manufacturer Part Number
ak4566vn
Description
20bit Stereo Codec With Built-in Ipga & Hp-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet
AKM CONFIDENTIAL
ASAHI KASEI
[AK4566]
n IPGA Operation
[Write Operation at ALC Enabled]
The values of IPGA6-0 bits are ignored during ALC operation.
[Write Operation at ALC Disabled]
Channel independent zero crossing detection is used. If there is no zero crossings, then the level will change after a timeout.
The ZTM1-0 bits set the zero crossing timeout. When the IPGA7-0 bits are written by P, the zero crossing counter is reset
and starts. When the IPGA output signal detects zero crossing or zero crossing timeout, the written value by P becomes
valid.
When writing to the IPGA7-0 bits continually, the control register should be written by an interval more
than zero crossing timeout. If not, there is a possibility that each IPGA of L/R channels has a different gain.
[IPGA Gain after completing ALC operation]
The IPGA7-0 bits are not updated by the actual gain of IPGA changed during ALC operation. In order to set the actual gain
of IPGA with the IPGA7-0 bits, the IPGA7-0 bits should be written after zero crossing timeout period when completing
ALC operation (ALC bit= “1” à “0”).
REV 0.5
2002/2
- 19 -

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