ak4566vn AKM Semiconductor, Inc., ak4566vn Datasheet - Page 22

• Manufacturer Part Number: ak4566vn
• Description: 20bit Stereo Codec With Built-in Ipga & Hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n Power-Up/Down Sequence
1) ADC
(1) PDN pin should be set to “H” at least 150ns after the power is supplied.
(2) HPLMT, HPRMT and PMVCM bits should be changed to “1” after PDN pin goes to “H”.
(3) PMADC bit should be changed to “1” after HPLMT, HPRMT and PMVCM bits are changed to “1”.
(4) External clocks (MCLK, BICK, LRCK) are needed to operate ADC. When PMADC= “0”, these clocks can be
(5) When PMADC bit is changed to “1”, each AIN pin is biased to VCOM voltage. Rising time constant is determined by
(6) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state. SDTO
(7) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385µs@fs=44.1kHz).
REV 0.5
stopped.
input capacitor for AC coupling and input resistance. In case of AINL2/AINR2 and 1µF input capacitor, time constant
is
is “L” at that time.
Power Supply
PDN pin
HPLMT,
PMVCM bit
Clock Input
PMADC bit
ADC Internal
AIN pin
SDTO pin
HPRMT bit
State
(1) >150ns
PD(Power-down)
(Hi-Z)
Don’t care
(3) >0
(2)
>0
Figure 17. Power-up/down sequence of ADC
(5)
(4)
(6) 2081/fs
Init Cycle
= 1µF x 12.5k = 12.5ms (typ)
AKM CONFIDENTIAL
(7) GD
Normal Operation
- 22 -
(7) GD
Don’t care
Don’t care
(Hi-Z)
PD
(6) 2081/fs
Init Cycle
Normal Operation
(7) GD
[AK4566]
2002/2