ak4566vn AKM Semiconductor, Inc., ak4566vn Datasheet - Page 31

• Manufacturer Part Number: ak4566vn
• Description: 20bit Stereo Codec With Built-in Ipga & Hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
REV 0.5
Addr
03H
LMTH: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 9)
RATT: ALC Recovery GAIN Step (Table 10)
LMAT1-0: ALC Limiter ATT Step (Table 11)
ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation
ALC: ALC Enable Flag
LMTH
Register Name
ALC Mode Control 1
0
1
Default
During the ALC recovery operation, the number of steps changed from current IPGA value is set. For
example, when the current IPGA value is 3FH, RATT = “1” is set, IPGA changes to 41H by the ALC
recovery operation, the output signal level is gained by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF6-0 bits), the IPGA value does not increase.
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by
LMTH bit, LMAT1-0 bits set the number of steps attenuated from current IPGA value. For example, when
the current IPGA value is 3FH in the state of LMAT1-0 bit = “11”, it becomes IPGA = 3BH by the ALC
limiter operation, the input signal level is attenuated by 2dB (=0.5dB x 4). When the attenuation value
exceeds IPGA = “00H” (Mute), it clips to “00H”.
0: Enable (Default)
1: Disable
In case of ZELMN = “0”, when IPGA output detects zero crossing or timeout, the IPGA value is changed by
ALC operation. Zero crossing timeout is the same as ALC recovery operation. In case of ZELMN = “1”, the
IPGA value is changed immediately.
0: ALC Disable (Default)
1: ALC Enable
ALC is enabled at ALC bit is “1”. Default: “0” (Disable).
ALC Limiter Detection Level
Table 9. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
ADC Input
ADC Input
LMAT1
6.0dBFS
4.0dBFS
0
0
1
1
Table 10. ALC Recovery Gain Step Setting
D7
Table 11. ALC Limiter ATT Step Setting
0
0
RATT
0
1
AKM CONFIDENTIAL
LMAT0
0
1
0
1
D6
0
0
GAIN STEP
ALC Recovery Waiting Counter Reset Level
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1
2
ALC
ATT STEP
D5
6.0dBFS
4.0dBFS
0
1
2
3
4
ZELMN
D4
0
ADC Input
ADC Input
Default
Default
LMAT1
D3
0
8.0dBFS
6.0dBFS
LMAT0
D2
0
RATT
D1
0
Default
[AK4566]
LMTH
2002/2
D0
0