ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 116

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

2.6.3 Synch. Signal Generation Adjustment Setting (for Demonstration)
OKI Semiconductor
ISYNC Initial value: 0; Setting range: 0 to 1
HSSEL Initial value: 0; Setting range: 0 to 1
SHSDL[7:0] Initial value: 0011_1111; Setting range: 0000_0001 to 1111_1111
Register name
Register name
SUB_ADDRESS=78h (W/R): Output system memory control mode setting
SUB_ADDRESS=79h(W/R): OHS generation start position setting
DATA_BIT
DATA_BIT
Sets the generation of an OVS/OHS internal Sync. signal.
* Since this is a setting for demonstration, normally set this bit to 0.
Sets internally generated OHS composite Sync.
* Since this is a setting for demonstration, normally set this bit to 0.
Set an OHS generation starting position of the internal Sync generator.
* Since this is a setting for demonstration, normally set this bit to 0.
Table R2-6-3(2) Internally Generated OHS Composite Sync Setting
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
BIT7
BIT7
Table R2-6-3(1) Internal Sync. Signal Generation Setting
7
BIT6
BIT6
HSSEL
ISYNC
6
0
1
0
1
BIT5
BIT5
5
Input (IVS, IHS)-delay output
Internally generated output
Horizontal Sync. signal
OVS, OHS output
Composite Sync
BIT4
BIT4
OHS phase
4
SHSDL
BIT3
BIT3
3
BIT2
BIT2
2
HSSEL
BIT1
BIT1
1
PEDL87V21071-01
ML87V21071
ISYNC
BIT0
BIT0
0
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