ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 18

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

OKI Semiconductor
• Setting of Input System Horizontal Valid Pixel Start Position
The input system horizontal valid pixel start position (IHPS) is set in pixel unit with reference to the input
system horizontal reset (IHR: internal signal), generated from IHS, by setting NPHWE[7:0]
(SUB:45h-bit[7:0]).
The data subsequent to IHPS is written in the data memory of valid pixels as the valid data.
This value can be set in 255 levels of ±127 pixels with regard to the initial value (NPHWE[7:0] = 80h).
In the ITU-R BT.656 mode, the value cannot be set. Write enable with regard to valid data is generated on the
basis of detected SAV, EAV.
[1]
0
0
0
0
1
1
Other than above
HMD
#IWE
CI[7:0]
YI[7:0]
[0]
IHS
0
0
1
1
0
0
Table F1-1-3 (5) Input System Horizontal Valid Pixel Start Position
Figure F1-1-3 (5) Input System Horizontal Valid Pixel Start Timing
VMD
[0]
0
1
0
1
0
1
127 pixels
17 (–127 pixels)
11 (–127 pixels)
49 (–127 pixels)
13 (–127 pixels)
49 (–127 pixels)
15 (–127 pixels)
NPHWE=01h
IHPS
1 pixel
127 pixels
IHPS position (Number of pixels from IHS)
……
……
……
……
……
……
……
Test modes (Setting inhibited)
640/720/768 pixels
NPHWE=80h
144 (default)
138 (default)
176 (default)
140 (default)
176 (default)
142 (default)
Valid data
……
……
……
……
……
……
……
271 (+127 pixels)
265 (+127 pixels)
303 (+127 pixels)
267 (+127 pixels)
303 (+127 pixels)
269 (+127 pixels)
NHPWE=FFh
PEDL87V21071-01
1 pixel
ML87V21071
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