ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 64

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

3. Other Functions
3.1 REF Pin Output
OKI Semiconductor
Set the I2C-bus setting register REFSL[1:0] (SUB:60h-bit[4:3]) to select a horizontal reference signal,
chrominance select signal, or effective area signal for output from the HREF pin.
YO[7:0]
CO[7:0]
• Horizontal reference signal
• Chrominance select signal
OCLK
OHS
ORE
HREF
This signal is a signal for default valid data period 1 and blanking period 0. This signal can be used as the
reference for separating Cb, Cr, etc.
The chrominance select signal is a signal that toggles between 0 (at valid period start) and ICLK. It can be
used as a signal for separating Cb and Cr.
[1]
0
0
1
1
REFSL
CO[7:0]
OCLK
HREF
[0]
0
0
1
0
1
1
BLK
2
Figure F3-1 (2) Chrominance Select Signal Timing
l pixels
3
Effective area signal (horizontal reference signal + vertical blanking signal)
Figure F3-1 (1) Horizontal Reference Signal
m: Set at VMD, HMD.
n: m/2
l: Set at NPHRE[7:0].
4
Table F3-1 REF Pin Output Selection
Cb
Y_BLK (00, 01, 08, 10)
Cr
l-1
C_BLK (80)
l
Cb
3 pixels
l+1
Output system filed pulse signal
Horizontal reference signal
Chrominance select signal
Cr
Horizontal valid data
l+2
l+3
REF pin output
Cb0 Cr0
Cb
Y0
period
Y1
Cr
Cb1 Cr1
Y2
Cb
Y3
m pixels
Cr
Ym-3
Cbn-1
Crn-1
Cb
Ym-2
Ym-1 Ym
Cbn
Cr
Crn
PEDL87V21071-01
Y_BLK (00,01,08,10)
BLK
ML87V21071
C_BLK (80)
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