ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 25

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

OKI Semiconductor
The data and control signal interfaces according to input system modes are as follows.
Input in 16-bit mode
#IICLK
YI[7:0]
CI[7:0]
ICLK
• Input in 16-bit mode
• Input in 8-bit mode
• ITU-R BT.656 mode
Vertical Sync. signal:
Horizontal Sync. signal:
Data input pin:
Input system clock frequency: f
Clip level:
Vertical Sync. signal:
Horizontal Sync. signal:
Data input pin:
Input system clock frequency: f
Clip level:
Vertical Sync. signal:
Horizontal Sync. signal:
Data input pin:
Input system clock frequency: f
Clip level:
* By setting POFF (SUB:41h-bit[6]) to 1, the parity bits of SAV and EAV can be disabled.
#: Internal signal
Cn
Yn
Yn+1
Cn+1
Figure F1-2-1 (1) Input Data Timing
Cn+2
Yn+2
IVS
IHS
YI[7:0], CI[7:0] (YCbCr-4:2:2)
None
IVS
IHS
YI[7:0], (YCbCr-4:2:2)
None
SAV, EAV split
SAV, EAV split
YI[7:0] (YCbCr-4:2:2)
00h → 01h, FFh → Feh
ICLK
ICLK
ICLK
Cn+3
Yn+3
= 12.2727272/13.5/14.31818/14.75 MHz
= 24.545454/27/28.63636/29.5 MHz
= 27 MHz
Input in 8-bit mode or ITU-R BT.656 mode
#IICLK
CI[7:0]
YI[7:0]
ICLK
Cbn
don't care (no connect)
Yn
Crn
PEDL87V21071-01
ML87V21071
Yn+1
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