ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 69

• Manufacturer Part Number: ml87v21071
• Description: Video Signal Noise Reduction Ic With A Built-in Frame Memory
• Manufacturer: Oki Semiconductor

3.6 Output Enable/Disable Setting
3.7 Release of Synchronization by Register Setting
OKI Semiconductor
By setting the OUTDS(SUB:72h-bit[1]) = 1, the output pins (YO[7:0], CO[7:0], OVS, OHS, HREF, CLKO) are
put in the Hi-Z state.
At system reset (external pin RESET = 0), all the output pins can be set to Enable/Disable by the external pin OE
regardless of the setting of OUTDS and output pin levels at power-on can be set.
By setting external pins OE and OEINV (SUB:72h-bit[3]), the output data pins (YO[7:0], CO[7:0]) can be put in
the Hi-Z state.
Normally, the data that is set through I
However, as a test mode, using the I
synchronization. Normally, synchronize with IVS by setting the register to 0.
*1: Fixed to 0 by system reset.
RST
1
1
1
1
1
0
0
OUTDS
Table F3-7 Synchronization Release Setting by Register
0 (*1)
0 (*1)
0
0
0
0
1
Table F3-6 Output Pin Enable/Disable Setting
OE
X
0
0
1
1
0
1
2
RLTG
C interface is reflected in the IC internal section synchronously with IVS.
0
1
2
C-bus setting register RLTG (SUB:72h-bit[7]) can release
OEINV
0 (*1)
0 (*1)
0
1
0
1
X
Synchronized with IVS
When set by I
Data reflection
Data output pin
Disable
Disable
Disable
Disable
Enable
Enable
Enable
2
C
Output pins other than data
Disable
Disable
Enable
Enable
Enable
Enable
Enable
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the