ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 27

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ml87v21071

Manufacturer Part Number
ml87v21071
Description
Video Signal Noise Reduction Ic With A Built-in Frame Memory
Manufacturer
Oki Semiconductor
Datasheet

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1.2.2 Output Data Format
* When input is ITU-R BT.656, Sync (H, V) on the output side is output to OVS and OHS as the Sync. signal
OKI Semiconductor
separated from SAV and EAV.
Since internal signal processing is performed independently for luminance and chrominance signals, the output
data format of basic output of this IC is YCbCr 16bit 4:2:2.
However, in YCbCr 8bit 4:2:2 mode and ITU-R BT.656 mode, selection of YCbCr 8bit 4:2:2 (same format as
input) is enabled by setting DOSEL (SUB:60h-bit[1]) to 1. In this case, unused CO[7:0] becomes Hi-Z.
Table F1-2-2(2) shows the delay amount from input to output and the same delay amount occurs for all the data
and Sync. signals.
DISEL
X
X
0
1
1
R656I
0
0
0
1
1
Output
YO7
YO6
YO5
YO4
YO3
YO2
CO7
CO6
CO5
CO4
CO3
CO2
CO1
CO0
YD1
YD0
Table F1-2-2(2) Combinations for Input/Output Data Format
DOSEL
X
0
1
1
0
Cb07
Cb06
Cb05
Cb04
Cb03
Cb02
Cb01
Cb00
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
Normal mode
Table F1-2-2 (1) Output Data Format
16-bit + Sync (H, V)
8-bit + Sync (H, V)
8-bit + Sync (H, V)
ITU-R BT.656
ITU-R BT.656
Cr07
Cr06
Cr05
Cr04
Cr03
Cr02
Cr01
Cr00
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
Input
8-bit input – 8-bit output mode (DOSEL =1)
Cr07
Cr06
Cr05
Cr04
Cr03
Cr02
Cr01
Cr00
ITU-R BT.656 + Sync (H, V)
16-bit + Sync (H, V)
16-bit + Sync (H, V)
8-bit + Sync (H, V)
8-bit + Sync (H, V)
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Output
Cb07
Cb06
Cb05
Cb04
Cb03
Cb02
Cb01
Cb00
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Input/output delay
PEDL87V21071-01
32 (ICLK)
64 (ICLK)
66 (ICLK)
64 (ICLK)
66 (ICLK)
amount
ML87V21071
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