ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 93
ml87v21071
Manufacturer Part Number
ml87v21071
Description
Video Signal Noise Reduction Ic With A Built-in Frame Memory
Manufacturer
Oki Semiconductor
Datasheet
1.ML87V21071.pdf
(123 pages)
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2.3.5 Noise Upper Limit Setting
OKI Semiconductor
SUB_ADDRESS = 4Eh(W/R): Luminance noise upper limit level setting
SUB_ADDRESS = 4Fh(W/R): Chrominance noise upper limit level setting
YLM[4:0] Initial value: 0_0110; Setting range: 0_0000 to 1_1111
AYNDL Initial value: 0; Setting range: 0 to 1
AYLM[1:0] Initial value: 00; Setting range: Refer to table R2-3-5 (1).
CLM[4:0] Initial value: 0_0011; Setting range: 0_0000 to 1_1111
AYNDL Initial value: 0; Setting range: 0 to 1
ACLM[1:0] Initial value: 00; Setting range: Refer to table R2-3-5 (2).
Register name
Register name
DATA_BIT
DATA_BIT
Sets luminance noise upper limit level.
The limit values are selected by 00h to 1Fh.
Sets luminance noise upper limit level of noise detection.
By setting 1, unexpected noise at noise detection is restricted to control the rapid change in the noise
detection amount.
Sets auto mode luminance noise upper limit level.
Becomes valid in noise follow-up state in the auto mode.
Sets chrominance noise upper limit level.
The limit values are selected by 00h to 1Fh.
Sets luminance noise upper limit level of noise detection.
By setting 1, unexpected noise at noise detection is restricted to control the rapid change in the noise
detection amount is controlled.
Sets auto mode chrominance noise upper limit level.
Becomes valid in the auto mode noise follow-up state.
BIT7
BIT7
1
1
AYLM
ACLM
BIT6
BIT6
0
0
AYNDL
ACNDL
BIT5
BIT5
BIT4
BIT4
4
4
BIT3
BIT3
3
3
BIT2
YLM
BIT2
CLM
2
2
BIT1
BIT1
1
1
PEDL87V21071-01
ML87V21071
BIT0
BIT0
0
0
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