ml87v21071 Oki Semiconductor, ml87v21071 Datasheet - Page 17

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ml87v21071

Manufacturer Part Number
ml87v21071
Description
Video Signal Noise Reduction Ic With A Built-in Frame Memory
Manufacturer
Oki Semiconductor
Datasheet

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#IWE/IRE
• Setting of Input System Vertical Valid Line Start Position
*1: In the case of field B, it is +1.
R656I
R656I
#IWE/IRE
YI[7:0]
CI[8:0]
#IVR
0
0
1
1
0
0
IVS
IHS
Table F1-1-3 (4) Input System Vertical Valid Line Start Position (INPR=1: Progressive)
The input system vertical valid line start position (IVPS) is set in line unit with reference to the input system
vertical reset (IVR: internal signal), generated from IVS, by setting NPVWE[4:0] (SUB:44h-bit[4:0]). Data of
valid lines is written in the memory taking the input data subsequent to IVPS as valid data.
For this value, ±7 lines (15 stages) can be set for the reference position (NPVWE[3:0]=8h) in interlace mode
(INPR=0) and in progressive mode (INPR=1), ±15 lines (31 stages) can be set for the reference position
(NPVWE[4:0]=10h).
In interlace mode, NPVWE[4] is ignored.
Other than above
YI[7:0]
CI[8:0]
#IVR
IVS
IHS
Table F1-1-3 (3) Input System Vertical Valid Line Start Position (INPR=0: Interlace)
[1]
[1]
0
0
0
0
0
0
Figure F1-1-3 (3) Input System Vertical Valid Line Start Timing (INPR=0)
Figure F1-1-3 (4) Input System Vertical Valid Line Start Timing (INPR=1)
VMD
VMD
: Valid data
: Valid data
[0]
[0]
0
1
0
1
0
1
17 (–7 lines) (*1)
12 (–7 lines) (*1)
#: Internal signal
24 (–15 lines)
12 (–15 lines)
#: Internal signal
13 (–7 lines)
NPVWE=1h
NPVWE=1h
7 (–7 lines)
15 lines
7 lines
IVPS position (number of IHS’s from IVR)
IVPS position (number of IHS’s from IVR)
……
……
……
……
……
……
……
……
IVPS
IVPS
Test modes (not settable)
24 (default) (*1)
19 (default) (*1)
NPVWE=10h
NPVWE=8h
20 (default)
14 (default)
49 (default)
27 (default)
15 lines
7 lines
576/486 lines
288/243 lines
……
……
……
……
……
……
……
……
31 (+7 lines) (*1)
26 (+7 lines) (*1)
54 (+15 lines)
42 (+15 lines)
NPVWE=1Fh
NPVWE=Fh
27 (+7 lines)
21 (+7 lines)
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ML87V21071
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