le79128 Zarlink Semiconductor, le79128 Datasheet - Page 13

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

HOST BUS INTERFACE (HBI) OVERVIEW
The Host Bus Interface provides a means for exchanging control, configuration, and status information with an external host
processor. The HBI is able to sustain 16-bit transactions up to 10 MHz rate with minimal latency.
This interface is implemented through a combination of hardware and firmware. The design is layered as shown in
Hardware provides a generic means for transporting data between the host and internal memory. The interpretation of the data
is provided by firmware running on the VCP. This layered architecture allows the definition of the application level interface to
change by modifying the firmware.
Transport Layer
The transport layer moves 16-bit data words between the physical interface and internal memory or registers on an internal bus.
It defines the structure of a transport frame, which consists of a 16-bit command word followed by 0 or more 16-bit payload data
words. It also defines the interface address model, and provides mapping between interface and internal addresses.
Application Layer
The application layer defines the programmer’s interface, and is almost entirely implemented in firmware. The exception is a
handful of configuration registers implemented in hardware. This layer defines the meaning of the payload data delivered by the
transport layer. Because it is implemented in firmware, the definition of the programmer’s interface can change by providing new
software.
Physical Layer
The physical layer provides the functionality needed to electrically interface with a host processor. It defines the pins, signal timing
and electrical characteristics of the interface. Two physical interfaces are provided. The General Purpose Parallel Interface (GPI)
implements an 8-bit or 16-bit wide parallel interface. Options are selected via the configuration pins, refer to
Peripheral Interface (SPI) implements a 4-wire synchronous serial slave interface.
The NG chipset (Le79271 SLIC, Le79238 SLAC, and Le79128 VCP) supports use of the GPI 16-bit interface.
Refer to the Next Generation Carrier Chipset Hardware Design Guide for connection diagrams.
Hardware
Firmware
Application Layer
Transport Layer
Physical Layer
GPI
Figure 3. Host Bus Interface Layers
SPI
Microsemi Corporation - CMPG
Le79128
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Provides the application programmer’s interface. Defines
the meaning of payload data passed over the interface.
Moves 16-bit data words between the physical layer and
internal memory.
Defines the pins, signal timing and electrical characteristics
of the interface.
Preliminary Data Sheet
Table
8. The Serial
Figure
3.