le79128 Zarlink Semiconductor, le79128 Datasheet - Page 22

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

AUTO_HIWAYAB
FSA_GEN
PCLKA_FREQ[12:0]:
Using FSA as an 8-kHz reference, the device will automatically select the correct PCLKA_FREQ
value. The initial PCLKA_FREQ[12:0] setting will be 1001011111011 (PCLKA=38.880 MHz). If the
FSA or PCLKA pulses are absent, the device will maintain CSEL[12:0] = 1001011111011 until it
detects transitions on both the FSA and PCLKA inputs. Automatic frequency detection will occur
after 9 consistent FSA periods. Meaning, reading this register before the mentioned 1.125ms will
report the default (0x92FB) PCLKA, not the actual PCLKA frequency.
If FSA is to be generated internally, set FSA_GEN bit to internal generation, set the AUTODETECTA
bit to 0 and write the appropriate clock frequency register PCLKA_FREQ[12:0] with the desired
value. This can be done in the Hardware Abstraction Layer (HAL) function used to initialize the chip
and configure the HBI interface. This should be done before booting the device.
Clock Status (CLKSTAT)
CFAIL_GLOBAL:
CFAIL_PCLKA:
CFAIL_PCLKB:
D15
D7
(RO)
(RO)
D14
(RO)
D6
PCLKA clock failure indicator.
PCLKB clock failure indicator.
RSVD
PLL failure indicator.
Indicates the set frequency of PCLKA as a multiple of 8KHz -1. When
0: Disable highway automatic switching option.
1: Automatically switch from Highway A to Redundant Highway if
FSA Generation.
0: FSA is provided externally.
1: FSA is generated by the VCP device at the specified frequency. When ever this
writing AUTODETECTA = 1, the default is restored to these bits
1001011111011 until the auto-detection is complete. PCLKA can be any
frequency that is a multiple of 512KHz +/- 6000ppm. The software
supports PCLK frequencies up to 8.192 MHz.
0000000111111:
0000010111111:
0000011111111:
0000111111111:
0001111111111:
0011111111111:
1000100111111:
1001011111011:
0: No Failure
1: PLL failure detected
0: No Failure
1: Clock failure detected
0: No Failure
Highway A to Redundant Highway Switch.
CFAIL_PCLKA=1 and CFAIL_PCLKB=0 (See CLKGEN_STATUS for definition
of CFAIL_PCLK)
bit is set to High. the AUTODETECTA bit should be set to Low.
Microsemi Corporation - CMPG
RSVD
D13
D5
Le79128
22
D12
D4
PCLKA = 512 kHz.
PCLKA = 1.536 MHz
PCLKA = 2.048 MHz.
PCLKA = 4.096 MHz.
PCLKA = 8.192 MHz.
PCLKA = 16.384 MHz.
PCLKA = 35.328 MHz ADSL clock
PCLKA = 38.880 MHz (default)
POR
D11
D3
Direct page address 0x0A (R/W)
GLOBAL
CFAIL
D10
RST
D2
Preliminary Data Sheet
PCLKB
CFAIL
WDT
D9
D1
HWRES
PCLKA
CFAIL
D8
D0