le79128 Zarlink Semiconductor, le79128 Datasheet - Page 30

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

GPI Timing Requirements
The timing requirements for read and write accesses are shown in the following timing diagrams. The PWAIT waveform on the
read diagrams is shown as a dotted line because the wait strobe feature is optional and would only go active if the read data was
not yet valid following a read command. Also, although the wait strobe polarity is programmable, it is shown as active Low in
several of the timing diagrams. Each write and read access is qualified by an active chip select signal. In some applications, the
chip select pin could be tied Low. The 16-bit accesses using separate read and write strobes is shown in
The 8-bit accesses using separate read and write strobes are shown in
and 16-bit figures using separate read and write strobes can be found in
write strobe and a data strobe is shown in
combined read/write strobe and a data strobe can be found in
register access (which applies to both 8 and 16-bit modes). It should be noted that if the host is using the wait strobe feature and
issues a read command, that performing a status read operation immediately after the writing of a read command and before the
actual read of the first byte/word of data would cause the read status access to be extended. Refer to
of the byte swap operation on the data word (which also applies to 8 and 16-bit modes).
Notes:
1.
2.
3.
4.
Refer to Figure 26 for timing diagram test points.
The Wait Strobe active edge may occur as early as the rising Write Strobe signal if Chip Select is held active.
The pin load is assumed to be C
This is the time between the read command and the first data word. If PWAIT is not used, then the maximum value must be met by the host.
If PWAIT is used, faster transactions can occur.
Table 15. GPI Bus Timing Parameters for Separate Read and Write Strobes
No.
10
11
1
2
3
4
5
6
7
8
9
t
HOLD_OUT
t
t
t
t
Symbol
WR_RDV
HOLD_IN
CS_WAIT
WAIT_DV
t
t
RD_DV
t
SU_IN
t
t
WAIT
t
ACC
OFF
ON
Access period (from Write to Write or Read to
Read or Read to Write)
Pulse width LOW (PCS or PWR or PRD)
Pulse width HIGH (PCS & PWR or PCS &
PRD)
Write to Read (rising PWR to Data output
valid)
PCS, PADDR, PRD active to Data output
valid
Address, Data input setup time to rising PCS
or PWR
Address, Data input hold time after rising
PWR or PCS
Data output hold time after rising PRD or
PCS
Chip Select active to Wait active
Wait strobe width LOW when PCS is active
PWAIT deserted to Data valid
load
= 75pF.
Figure 11
Parameter
Microsemi Corporation - CMPG
and
Le79128
Figure
30
Table
12. The timing information for the 8 and 16-bit figures using a
16. Refer to
Figure 9
Table
Min
100
35
10
25
15
—
—
—
0
0
0
15. The 8-bit accesses using a combined read/
and
Figure 13
Figure
Typ
80
—
—
—
—
—
—
—
—
—
—
1
.
10. The timing information for the 8
for an example of the read status
Preliminary Data Sheet
Max
270
280
—
—
—
25
—
—
10
25
0
Figure 14
Figure 7
Unit
ns
for an example
and
Note
Figure
3,4
2,3
2,3
3
3
2
8.