le79128 Zarlink Semiconductor, le79128 Datasheet - Page 43

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

PCM INTERFACE
Two PCM blocks reside on the Le79128 device. There is a Slave PCM Highway A/Redundant block comprised of the PCLKA,
FSA, DXA, DRA, TSCXA, TSCRA, PCLKB, FSB, DXB, DRB, TSCXB, and TSCRB pins, and a block used as the Slave PCM
Highway B comprised of the MPCLK, MFS, MDX, and MDR pins. The Slave PCM Highway A/Redundant block requires PCLKA
or PCLKB as inputs. The Slave PCM Highway B requires MPCLK as an input. In hardware, MPCLK and MFS can be configured
as outputs, therefore specifications for output use are provided in
Hardware Design Guide for diagrams on supported PCM Highway usage.
The Redundant highway is useful if the A highway suffers a system failure. PCLKA and PCLKB are closely monitored by
CLKGEN to perform an automatic highway switch (if desired) when the selected highway fails.
The Slave PCM Highway A/Redundant block provides backplane driver tristate control outputs TSCXA and TSCXB when DXA
or DXB are active respectively. The Slave PCM Highway B block does not have a redundant backup or the tristate control outputs.
Timing for these blocks is shown in
No.
10
12
11
1
2
3
4
5
6
7
8
9
Table 20. PCM Interface Timing Parameters
Symbol
t
t
t
t
t
t
MPCF
MPCR
t
t
t
t
t
t
t
t
TSCD
TSCZ
t
t
t
DOH
t
PCY
PCH
PCR
DOZ
PCL
PCF
FSD
FSS
FSH
PCT
FST
DIS
DIH
PCLKx or MPCLK period
PCLKx or MPCLK HIGH pulse width
PCLKx or MPCLK LOW pulse width
Fall time of PCLKx (Input)
Rise time of PCLKx (Input)
Fall time of MPCLK (Output)
Rise time of MPCLK (Output)
FS delay (Output rising or falling)
FS setup time (Input)
FS hold time (Input)
Data output hold time
Data output delay to high-Z
TSC output delay
TSC output delay to high-Z
Data input setup time
Data input hold time
Allowed PCLK jitter time
Allowed Frame sync jitter time
Figure 24
Parameter
and
Microsemi Corporation - CMPG
Table
20. PCLK accuracy = ± 100 PPM.
1
Le79128
43
-t
Min.
PCY
122
–97
61
24
48
24
48
11
10
10
—
—
—
—
0
0
0
2
2
5
5
5
5
Table
/2
20. Refer to the Next Generation Carrier Chipset
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1953.1
1953.1
t
t
PCY
PCY
Max
15
25
16
25
10
16
25
10
97
—
—
—
—
—
—
—
8
8
8
8
–2
/2
Preliminary Data Sheet
Unit
ns
2,4,6,7
2,5,6,7
Note
10
10
4
5
4
5
4
5
4
5
3
4
5
9
9
7
8