le79128 Zarlink Semiconductor, le79128 Datasheet - Page 18

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

Direct Page (Hardware) Registers
This section details each of the VoiceEdge VCP device registers provided by the hardware or boot firmware. These registers are
provided for debugging purposes only. The VP-API has corresponding definitions for their addresses (and bit definitions) and
knows how to read/write these registers.
Note:
In all registers, "RSVD" should be written 0 and reads as indeterminate, unless otherwise indicated.
Interrupt Indication (INTIND)
This register reports the source information for the current interrupt. It returns 0x0000 if there is no
active interrupt. Reading this register clears the associated interrupt and loads the INTPARAM
register with the associated parameter. In most cases the host should read the INTPARAM register
after reading this register. This can be accomplished with one multi-word read, since the INTPARAM
register immediately follows the INTIND register.
INT_SRC
INT_IND[14:0]
Interrupt Parameter (INTPARAM)
This register returns the parameter for the last interrupt read from the INTIND register. It is updated
whenever the INTIND register is read. Reading this register does not change the state of the
interrupt hardware.
INT_PARAM[15:0]
INT_SRC
D15
D15
D7
D7
D14
D14
D6
D6
Interrupt indication field. The contents of this field depend on the interrupt
Interrupt parameter field. The meaning of this field depends on the
Interrupt source bit.
0: Event queue.
1: System interrupt register.
source bit. If the INT_SRC indicates a system interrupt, each subsequent
bit indicates a transition on the corresponding system interrupt status
register bit (refer to the SYSINTSTAT register for details). Only unmasked
system interrupts will appear in this manner. If INT_SRC is 0, an
application specific interrupt is present.
associated interrupt. System interrupts will mirror the system interrupt
status (SYSINTSTAT) register at the time the INTIND read occurred.
Microsemi Corporation - CMPG
D13
D13
D5
D5
Le79128
18
D12
D12
D4
D4
INT_PARAM[15:8]
INT_PARAM[7:0]
INT_IND[7:0]
INT_IND[14:8]
D11
D11
D3
D3
Direct page address 0x00 (RO)
Direct page address 0x01 (RO)
D10
D10
D2
D2
Preliminary Data Sheet
D9
D1
D9
D1
D8
D0
D8
D0