r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 141

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
3.4.3.5 BRDY Interrupt Timing Selection Function
R e v 1 . 0 1
The PIPECFG register BFRE bit can be set so that the BRDY interrupt is not generated when a data packet of
maximum packet size is received.
When using a DMA transfer, this function enables an interrupt to be generated only when the last data is received. The
last data indicates either a short packet receive or the transaction count end. By setting “BFRE=1”, the BRDY interrupt
will be generated after the received data is read. By reading the DnFIFOCTR register DTLN bit, the receive data length
of last data packet received just before the BRDY interrupt was generated can be confirmed.
Table 3.20 shows the timing of the BRDY interrupt.
The BFRE bit function is only valid in the read direction of the buffer memory. When in the write direction, fix the
BFRE bit to “0”.
Buffer state when packet received
Buffer full (normal packet received)
Zero-Length packet received
Normal short packet received
Transaction count end
O c t 1 7 , 2 0 0 8
p a g e 1 4 1 o f 1 8 3
Registration Setting
Table 3.20 BRDY Interrupt Generation Timing List
When packet is received
When packet is received
When packet is received
When packet is received
BFRE = “0”
No interrupt generated
When packet is received
When read event of data received
from buffer memory is completed
When read event of data received
from buffer memory is completed
BFRE = “1”