r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 49

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
Remarks
* The interrupt enabled by the INTENB2 register can be written to only when the Host Controller function is selected. Do not
enable it when the Peripheral Controller function is selected.
2.9.1
R e v 1 . 0 1
♦ Interrupt enabled register 2 [INTENB2]
OVRCRE BCHGE
10-7 Unassigned. Fix to "0".
5-0 Unassigned. Fix to "0".
Bit
15
14
13
12
11
6
15
0
-
OVRCRE
Port1 OVRCR interrupt enabled
BCHGE
Port1 USB bus change interrupt
enabled
Unassigned. Fix to "0".
DTCHE
Port1 detach detect interrupt enabled
ATTCHE
Port1 attach detect interrupt enabled
EOFERRE
Port1 EOF error detect interrupt
enabled
Interrupt enabled registers 0, 1, 2 (INTENB0, INTENB1, INTENB2)
When the controller detects the interrupt corresponding to the bit for which the software has written "1" to the register,
the controller asserts an interrupt from the INT_N pin.
The controller sets "1" to this status bit corresponding to the INTSTS0, INTSTS1 and INTSTS2 registers when the
detection conditions of each interrupt factor are satisfied, irrespective of the setup value of the register (interrupt
notification disabled/enabled).
When the status bit of the INTSTS0, INTSTS1 and INTSTS2 registers corresponding to each interrupt factor are set to
"1", if the software modifies the interrupt enabled bit corresponding to the register from "0" to "1", the controller asserts
the interrupt from the INT_N pin.
14
O c t 1 7 , 2 0 0 8
0
-
13
?
?
Name
DTCHE
12
0
-
p a g e 4 9 o f 1 8 3
ATTCHE
11
0
-
10
?
?
Specify INT_N assert disabled/enabled while
detecting Port1 OVRCR interrupt.
0: Interrupt output disabled
1: Interrupt output enabled
Specify INT_N assert disabled/enabled while
detecting Port1 BCHG interrupt.
0: Interrupt output disabled
1: Interrupt output enabled
Specify INT_N assert disabled/enabled while
detecting Port1 DTCH interrupt (enabled only if
HOST).
0: Interrupt output disabled
1: Interrupt output enabled
Specify INT_N assert disabled/enabled while
detecting Port1 ATTCH interrupt.
0: Interrupt output disabled
1: Interrupt output enabled
Specify INT_N assert disabled/enabled while
detecting Port1 EOFERR interrupt.
0: Interrupt output disabled
1: Interrupt output enabled
9
?
?
8
?
?
Function
7
?
?
EOFERRE
6
0
-
5
?
?
4
?
?
Software Hardware Remarks
R/W
R/W
R/W
R/W
R/W
3
?
?
2
?
?
R
R
R
R
R
<Address: 34H>
1
?
?
"0" when
"0" when
"0" when
"0" when
"0" when
(Write to
(Write to
(Write to
(Write to
(Write to
P)"
P)"
P)"
P)"
P)"
H
H
H
H
H
0
?
?