r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 62

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
2.11.21.2 Writing "BRDYM=0" and "BFRE=1"
2.11.21.3 Writing "BRDYM=1" and "BFRE=0"
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transfer status stage.
The software can write to (clear) the PIPEBRDY interrupt status of the pipe to "0" by writing "0" to the bit
corresponding to the pipe of this bit. Here, write "0" to the bits corresponding to other pipes. Clear the interrupt status
before accessing the FIFO buffer.
If writing these, when the controller reads all the data of one transfer in reception pipe, it is determined that a BRDY
interrupt was issued and "1" is set in the bit corresponding to the pipe of register. In either of the following conditions,
it is determined that the controller receives the final data in one transfer:
(1) When a short packet, including a zero-length packet, is received
(2) When a packet of TRNCNT bit setup value is received by using transaction counter (TRNCNT bit)
When this data is read after fulfilling the above-mentioned determination conditions, the controller concludes that the
entire data of one transfer is read.
If a zero-length packet is received when the FIFO buffer is empty, the controller concludes that the entire data of one
transfer is read when a zero-length packet on CPU side is toggled. In this case, to start the next transfer by using the
software, write "1" to the BCLR bit of corresponding FIFOCTR register.
If writing these, the controller does not detect BRDY interrupt for the transmission pipe.
The software can write to (clear) the PIPEBRDY interrupt status of the pipe to "0" by writing "0" to the bit
corresponding to the pipe of this bit , and by writing "1" to the bit corresponding to other pipe.
While using this mode, do not modify the setup value of BFRE bit until the transfer process is completed. While
modifying BFRE bit during the process, clear all the FIFO buffers of the corresponding pipe by ACLRM bit.
If writing these, the bit value is coupled with the pipe’s BSTS bit. In other words, the controller sets "1" or "0"
depending on the FIFO buffer status of BRDY interrupt status.
(1) When the pipe is set to transmit. Sets "1" when the data can be written in the FIFO port, otherwise sets "0".
However, the BRDY interrupt is not asserted even if the DCP transmission pipe can be written to.
(2) When the pipe is set to receive. Sets "1" when the data can be written in the FIFO port, and "0" when all the data
is read (status changed to "Read disabled" status).
When the FIFO buffer is empty and a zero-length packet is received, "1" is set in the corresponding bit until the
software writes "BCLR=1", and the BRDY interrupt is asserted."
If writing these, the software cannot write "0" to this bit.
If writing "BRDYM=1", write "0" to all the BFRE bits (all pipes). If writing "BRDYM=1", write "1" to the INTL bit (level
control).
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