r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 46

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
2.8.17 CPU buffer clear bit (BCLR)
2.8.18 FIFO port ready bit (FRDY)
2.8.19 Reception data length bit (DTLN)
R e v 1 . 0 1
In this bit, the controller shows if access is possible to the FIFO port from the CPU (DMAC).
In the following cases, the controller sets "FRDY=1", but cannot read the data from the FIFO port since the data is not
available. In these cases, write "BCLR=1", clear the FIFO buffer, and then change the status to Data Send/Receive.
(1) If a zero-length packet is received when the FIFO buffer assigned to the specified pipe is empty.
(2) If "BFRE=1" is written, when the short packet is received and the data is read.
The controller sets the reception data length in this bit. The value of this bit changes according to the setup value of the
RCNT bit during the FIFO buffer read.
(1) When "RCNT=0":
(2) When "RCNT=1":
When the data on one side of the FIFO buffer is read, the controller sets "DTLN=0". However, when the double buffer
is set, and when data is received in the FIFO buffer on one side before reading the reception data on other FIFO buffer,
the reception data on one side is set in the DTLN bit when read on the first side is being completed.
When "RCNT=1", while reading the value of this bit during FIFO buffer read, the controller sets the updated value of
this bit up to150ns after the read cycle of the FIFO port.
If "1" is written to this bit, the controller clears the FIFO buffer on the CPU side from the FIFO buffers assigned to the
specified pipe.
When the setting of the FIFO buffer assigned to the specified pipe is a double buffer, the controller clears the FIFO
buffer only on one side, though the buffers on both sides can be read.
When the specified pipe is DCP, the controller clears the FIFO buffer when "BCLR=1", irrespective of the CPU or SIE
side. To clear the buffer on the SIE side, write "BCLR=1" after writing "NAK" to the PID bit.
When the specified pipe is transmitting, if "1" is written simultaneously to the BVAL and BCLR bits, the controller
clears the data written previously and changes the status of the zero-length packet to transmission possible.
If the specified pipe is not DCP, write "1" to this bit when the controller sets "FRDY=1".
The controller sets the reception data length in this bit until the CPU (DMAC) reads all the reception data on one
side of the FIFO buffer. When "BFRE=1", the controller holds the reception data length until "BCLR=1", although
the data is read.
The controller counts the DTLN bit display during each data read (counts down by -1 when "MBW=0", and by -2
when "MBW=1").
O c t 1 7 , 2 0 0 8
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