r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 44

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
2.8.10 Buffer pointer rewind (REW)
2.8.11 Auto FIFO buffer clear disabled/enabled bit (DCLRM)
2.8.12 DREQx_N output disabled/enabled bit (DREQE)
2.8.13 DxFIFO port access bit width (MBW)
2.8.14 Control bit of DxFIFO port byte endian (BIGEND)
2.8.15 FIFO port access pipe specification bit (CURPIPE)
R e v 1 . 0 1
Write the DxFIFO port access bit width in this bit. Refer to 2.8.5 for details.
Write the DxFIFO port byte endian in this bit. Refer to 2.8.2 for details.
Write the pipe number for the data to be read or written through the DxFIFO port.
To modify this bit, first write the data to this bit and then read it. Check if the write value matches the read value and
then proceed to the next process.
Do not write the same pipe to the CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers’ CURPIPE.
When this bit is modified during access to the FIFO buffer, access up to then is saved. Access to the buffer can be
continued after rewriting.
When the specified pipe is receiving, if "1" is written to this bit during the FIFO buffer read, the read can be started from
the initial data of the FIFO buffer (for a double buffer, during the read process, the initial data on one side can be read
again). When the software writes "1" to this bit, the controller again writes "0" to this bit.
Do not write "REW=1" and modify the CURPIPE bit. First check "FRDY=1" and then write "REW=1". While accessing
DxFIFO by writing "1" to the BFRE bit, do not write "1" to this bit when the short packet data is read.
Use the BLCR bit while rewriting the initial data of the FIFO buffer for the transmission pipe.
After reading the specified pipe data, set disabled/enabled for the auto FIFO buffer clear. When "1" is written to this bit,
the controller executes a "BCLR=1" process of the FIFO buffer if a zero-length packet is received when the FIFO buffer
assigned to the specified pipe is empty, or when the short packet reception data is read if writing "BFRE=1".
If "BRDYM=1" is written when using this controller, make sure to write "0" to this bit.
Write this bit so that the DxREQ_N signal output can be disabled/enabled.
When the DxREQ_N signal output is enabled, write "1" to this bit after writing to the CURPIPE bit. Write "0" to this bit
and then modify the CURPIPE bit.
O c t 1 7 , 2 0 0 8
p a g e 4 4 o f 1 8 3