cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 113

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
0x30—EN_CELL_INT (Enable Cell Interrupts)
The EN_CELL_INT register (0x30) enables interrupts for the CELL_STATUS register (0x3B). Setting a bit in
EN_CELL_INT enables each interrupt condition to appear on STAT_INT (pin 64).
0x32—TX_K1K2 (Transmit K1 and K2 Value)
The TX_K1K2 register (0x32) contains the APS Transmit K1 and K2 values.
0x33—RX_K1K2 (Receive K1 and K2 value)
The RS_K1K2 register (0x33) contains the APS Receive K1 and K2 values.
100046D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15-8
7-0
15-8
7-0
Bit
Bit
Bit
Field
Field
Field
Size
Size
Size
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
8
8
8
Cell Sent Cntr Ovfl–Port 3
Cell Sent Cntr Ovfl–Port 2
Cell Sent Cntr Ovfl–Port 1
Cell Sent Cntr Ovfl–Port 0
Cell Rcvd Cntr Ovfl-Port 3
Cell Rcvd Cntr Ovfl-Port 2
Cell Rcvd Cntr Ovfl-Port 1
Cell Rcvd Cntr Ovfl-Port 0
Cell Rcvd–Port 3
Cell Rcvd–Port 2
Cell Rcvd–Port 1
Cell Rcvd–Port 0
Cell Sent–Port 3
Cell Sent–Port 2
Cell Sent–Port 1
Cell Sent–Port 0
TX_K1
TX_K2
RX_K1
RX_K2
Name
Name
Name
Value to transmit in the K1 byte of the SONET frame.
Value to transmit in the K2 byte of the SONET frame.
Value of the last K1 byte received in the SONET frame. A change in this value causes
Bit 12 of the EVENT_STATUS register to be set.
Value of the last K2 byte received in the SONET frame. A change in this value causes
Bit 12 of the EVENT_STATUS register to be set.
Enables an interrupt if the CELL_SENT_CNT3 counter overflows.
Enables an interrupt if the CELL_SENT_CNT2 counter overflows.
Enables an interrupt if the CELL_SENT_CNT1 counter overflows.
Enables an interrupt if the CELL_SENT_CNT0 counter overflows.
Enables an interrupt if the CELL_RCV_CNT3 counter overflows.
Enables an interrupt if the CELL_RCV_CNT2 counter overflows.
Enable an interrupt if the CELL_RCV_CNT1 counter overflows.
Enables an interrupt if the CELL_RCV_CNT0 counter overflows.
Enables port 3 header match interrupt.
Enables port 2 header match interrupt.
Enables port 1 header match interrupt.
Enables port 0 header match interrupt.
Enables an interrupt when a cell is transmitted from port 3.
Enables an interrupt when a cell is transmitted from port 2.
Enables an interrupt when a cell is transmitted from port 1.
Enables an interrupt when a cell is transmitted from port 0.
Conexant
Description
Description
Description
3.6 Interrupt Enable Control Registers
3.0 Registers
3-27