cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 65

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
100046D
Table 2-19. Status Octet Definition
Table 2-20. PT Header Field and User Data Bit
Port X [bits 7–4] of CONFIG_4 [0x29] are not set, then enabled checks are made
on each cell received in the following sequence:
If Disable Cell Receiver [bit 14] of CELL_VAL and Disable Port Reception—
1.
2.
3.
The HEC is checked for errors under control of the HEC Coverage [bit 1]
of CONFIG_3 [0x03]. Correctable errors are corrected if Enable HEC
Correction [bit 8] of CELL_VAL is set. The correction/detection state
machine is implemented as defined in the ATM UNI/NNI specifications.
Errors counted in either the COR_HEC_ERR counter [0x49] or
UNCOR_HEC_ERR counter [0x4A] are also indicated in the
corresponding bits in the EVENT_STATUS register [0x39]. HEC error
correction/detection is performed independent of any header screening that
is enabled. Error correction should be enabled only if HEC Coverage is 0
and Enable HEC Coset [bit 0] of CONFIG_3 is 1.
The payload CRC-10 is checked. Errors are counted in the
PAY_CRC_ERR counter [0x48] and indicated in EVENT_STATUS. No
CRC checking is performed on cells matching the idle header description.
The payload length is checked to be consistent with the segment type.
Bit
0
1
2
3
4
5
6
7
PT Header Field
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Conexant
HEC Error Corrected for Port 3
HEC Error Not-Corrected for Port 3
Payload Length Error for Port 3 (AAL3/4)
Payload CRC-10 Error for Port 3 (AAL3/4)
User Data Bit for Port 3 (AAL5 EOM)
Header Match Port 0
Header Match Port 1
Header Match Port 2
Definition
User Data Bit
2.0 Functional Description
2.6 ATM Cell Processing
0
1
0
1
0
0
0
0
2-31