cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 140
cn8223
Manufacturer Part Number
cn8223
Description
Atm Transmitter/receiver With Utopia Interface
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8223.pdf
(161 pages)
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4.0 Electrical and Mechanical Specifications
4.3 Timing
4.3.2 Line Interface Timing
Table 4-3. Line Interface Timing—DS1, E1, DS3, E3 External Framers
4-6
NOTE(S):
(1)
(2)
Name
t txcki
t ckd1
t ckd2
t rxcki
t rsck
t ckrs
t rdck
t ckdr
t tsck
t ckts
t rxh
t txh
Nominal clock periods are:
Duty cycle must be 40/60 at maximum input clock rate.
Interval
11–12
10–11
11–14
8–13
8–11
9–11
1–7
1–4
3–4
4–6
1–2
4–5
DS1 –648 ns
E1 –488 ns
E3 –29.1 ns
DS3 –22.4 ns
Transmit Clock Period
Transmit Clock Pulse Width High
Transmit Sync Setup to Transmit Clock Falling Edge
Transmit Sync Hold after Transmit Clock Falling Edge
Transmit Clock Rising Edge to DS1/E1 Serial Data Out
Transmit Clock Falling Edge to DS3/E3 Serial Data Out
Receive Clock Period
Receive Clock Pulse Width High
Receive Sync Setup to Receive Clock Falling Edge
Receive Sync Hold after Receive Clock Falling Edge
Receive Data Setup to Receive Clock Falling Edge
Receive Data Hold after Receive Clock Falling Edge
Tables 4-3
requirements and characteristics of the line interfaces and parallel data and
overhead ports. All times are in nanoseconds. Example LIU circuits are provided
in CN8223 EVM schematics.
through
(1)
Description
4-6
Conexant
(2)
and
(2)
Figures 4-2
ATM Transmitter/Receiver with UTOPIA Interface
through
4-5
display the timing
Min
8.8
2.4
2.9
2.9
8.8
3.4
2.3
2.6
22
22
0
0
Max
12.2
10.4
100046D
—
—
—
—
—
15
—
—
—
—
CN8223
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