cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 49

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.3.4 STS-1 and STS-3c/STM-1 Modes
Table 2-12. STS-1, STS-3c, and STM-1 Overhead Values (1 of 2)
100046D
A1, A2
C1
B1
E1
F1
D1–D3
H1, H2, H3
Overhead Byte
Inserts standard values (0xF6, 0x28) or may be inserted externally through port TXOVH[7:0]. If this
bit is disabled, the value is 0x00.
Internally generated (0x00 if disabled; 0x01 in STS-1 mode; 0x01, 0x02, and 0x03 in STS-3c mode).
Can be externally inserted through port TXOVH[7:0].
Calculates and inserts B1. Errors can be inserted using the TXFEAC_ERRPAT register. Allows single
error insertion or all-zero value (continuous error).
Always inserted through port TXOVH[7:0].
Always inserted through port TXOVH[7:0].
Inserted externally through port TXOVH[7:0] or from internal HDLC formatter, if enabled.
Internally generated. The H1 values are 0x62 in STS-3c mode and 0x6A in STM-1 mode. The H2
value is 0x0A in both STS-3c and STM-1 modes. The H3 value is 0x00. If overhead insertion is
disabled, all values are 0x00.
All framing overhead is generated automatically and all BIP overhead is
calculated and inserted in the proper positions. BIP fields can be errored using the
TXFEAC_ERRPAT register [0x03] and BIP Error Insert [bits 12–10] of
CONFIG_2 [0x01]. Groups of overhead octets can be disabled (set to all 0s) using
Overhead Control [bits 3–0] of CONFIG_2. Internally generated octets are A1,
A2, C1, B1, B3, C2, H1, H2, H3, G1, B2, K2, H4, and M1.
then columns 30 and 59 in the payload envelope are stuffed with all 0s and are not
available for ATM cell octet transport (resulting in a total of 84 columns available
for transport). If this bit is not set, then all 86 columns of the SPE are available for
ATM cell octets.
setting Enable External Section Trace [bit 1] of CONFIG_4 [0x29]. The C1
values generated are listed in order of precedence in
Table 2-11. C1 Values
STM-1/STS-3c Pointer [bit 0] in the CONFIG_4 register [0x29]. This bit should
be set low for STS-1 operation. When this bit is low, the H1/H2 pointer value is
fixed at 0x620A. When this bit is set high (for STM-1 operation), the AU-4
pointer value is fixed at 0x6A0A (SS bits = 10). Overhead generation of STS-1,
STS-3c, and STM-1 values is summarized in
Disable C1
Enable External
STS-1 Mode
STS-3c/STM-1 Mode
In STS-1 mode, if STS-1 Stuffing Option [bit 15] in CONFIG_1 [0x00] is set,
The C1 octet can be programmed to be obtained from the TXOVH bus by
The pointer value generated in SONET/SDH modes is controlled by
Mode
Conexant
CN8223 Operation
Config_2[0]
Config_4[1]
Config_1[2:0]
Config_1[2:0]
Control Bit
Table
2-12.
Table
2.0 Functional Description
2-11.
2.3 Overhead Generation
00
From TXOVH Bus
01
01,02,03
C1 Octet Value
2-15