cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 56

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.5 Parallel Line Interface
2.5.1 TAXI Interface
2-22
2.5 Parallel Line Interface
The CN8223 has a parallel line interface consisting of TXOUT[8:0] and
RXOUT[8:0]. These octet ports allow interfacing of external framers or other
devices that use parallel data.
interface. Also, this interface can be used for the Advanced Micro Devices TAXI
interface chipset.
The parallel port of the CN8223 can be configured to interface directly with
AMD’s TAXI transmit/receive chipset. To enable this mode, set the following
values in each of these registers:
TAXI transmitter to insert JK sync and TT start-of-cell symbols before each
transmitted data cell of 53 octets. When no transmit port is active, the transmitter
sends continuous JK sync symbols.
synchronizes its cell circuitry to receive and process the 53-octet cell data. The
receiver ignores all incoming JK sync signals while awaiting the reception of the
TT symbol. The receiver is not clocked on any command or data octet if the
violation indication is present on RXIN[8]. None of the indications in the
LINE_STATUS register [0x38] are valid in TAXI mode except for One Second
Count. Any other indications should be ignored. Violations will be counted in
Line Counter 2. All cell status and cell event counters operate as in other modes.
interface is lost because of the use of the RCV_HLD pin. In this mode, the control
bits in CELL_VAL or external logic using the VLTN signal must be employed for
this function.
NOTE:
The transmit interface logic automatically generates the signals needed by the
The receiver interface logic detects the TT start-of-cell command and
In TAXI mode, the capability to shut down the output of cells to the FIFO
Source and line loopbacks are not functional in TAXI mode due to the
asymmetry between the transmit and receive control lines.
CONFIG_1 (0x00): Set the 8 LSBs to 0xE0.
CONFIG_3 (0x02): Set Enable HEC Coset (bit 0) and Invert RX Clock
CONFIG_4 (0x29): Set Enable TAXI Interface (bit 3) high.
Conexant
Table
(bit 8) high.
ATM Transmitter/Receiver with UTOPIA Interface
2-1, illustrates the architecture of this parallel
100046D
CN8223