cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 132

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

8223_031
Accept/Reject Header - Port 1
Accept/Reject Header - Port 0
Disable Length Check - Port 3
Disable Length Check - Port 2
Disable Length Check - Port 1
Disable Length Check - Port 0
Accept/Reject Header - Port 3
Accept/Reject Header - Port 2
Disable CRC Check - Port 3
Disable CRC Check - Port 2
Disable CRC Check - Port 1
Disable CRC Check - Port 0
Enable External Overhead
Latching of Line Counters
Invert RX Clock Sampling
Latching of Line Status
External 8-kHz Timing
STS-1 Stuffing Option
Receiver Hold Enable
Enable One-second
Enable One-second
HEC OCD Anomaly
Count Block Errors
Source Loopback
Receive G1 Bit 6
Receive G1 Bit 5
All-zeros FEBE
Software Reset
All-ones FEBE
Line Loopback
Reserved
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
CONFIG_1 (0x00)
CONFIG_2 (0x01)
CONFIG_3 (0x02)
CONFIG_4 (0x29)
CONFIG_5 (0x31)
0
0
0
0
0
PHY Type
Unframed Input
Disable B3ZS/HDB3
External Framer
Enable Parallel Interface
Disable LOCD
Enable Cell Scrambler
Overhead Control
BIP Error Insert
STM-1/STS-3c Pointer
Enable HEC Alignment
Transmit Alarm Control
Enable HEC Coset
HEC Coverage
Enable DS1 PRS Generator
Disable Write Strobes on Invalid Cells
Check Input Parity
Parity Odd/Even
Force Cycle Stuffing/Tx Overhead Control
Invert TX Clock Output
Enable External Section Trace
Delete Idle Cells
Enable TAXI Interface
Disable Port Reception - Port 0
Disable Port Reception - Port 1
Disable Port Reception - Port 2
Disable Port Reception - Port 3
Transmit Clock Select
Enable External Signal Label
Transmit G1 Bit 6
Transmit G1 Bit 5
Integrate HEC Framing
Enable HDLC Data Link
Set G1 X Bits All Ones
PHY Type
0 - DS1
1 - E1
2 - DS3
3 - 751 E3
4 - 804 E3
5 - E4
6 - STS1
7 - STS3
Inhibit Single Cell Generation
Enable FEAC Transmission
Disable Payload CRC
Transmit FEAC Data
Error Payload CRC
Disable HEC
Insert CLP
Error HEC
Insert VCI
Reserved
Reserved
Insert PT
Header and Mask Registers (0x15–0x1C, 0x1D–0x24)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2
15 14 13 12 11 10 9 8 7 6 5 4 3 2
15 14 13 12 11 10 9 8 7 6 5 4 3 2
15 14 13 12 11 10 9 8 7 6 5 4 3 2
TX_RATE Registers (0x08, 0x09)
CELL_GEN_x (0x04–0x07)
TXFEAC_ERRPAT (0x03)
IDLE_PAY (0x2A)
1 0
1 0
1 0
1 0
0
Idle Cell Payload Octet
Error Insertion Pattern
Enable Receive FEAC Interrupt
Insert VPI
Cell Generation Mode
1 0
0 0
0 1
1 0
1 1
Port Priority
Insert GFC
Rate Value - Port 2
Rate Value - Port 3
Rate Value - Port 0
Rate Value - Port 1
Header Octet 1
Header Octet 2
Header Octet 3
Header Octet 4
Enable Idle Cell CRC Insertion
48 Octet
52 Octet
53 Octet
57 Octet