cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 46

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.2 Line Framers
Figure 2-11. Receiver DS1 Line Interface Timing
2-12
RXDATI
RXCKI
RXSYI
7
8
S
falling edge of the input clock; and the low-to-high transition of the sync signal
occurs during the interval of the frame bit for DS1 and DS3, with the first bit of
time slot 0 for E1, and the first bit of the frame-alignment signal for E3. For
brevity, only the DS1 timing is illustrated
interface is similar to the timing on the transmit interface. It is compatible with
Conexant framers. The data and sync inputs can be sampled on the rising edge of
the input clock by setting Invert RX Clock Sampling [bit 8] of CONFIG_3
[0x02].
ignored. RXSYI does not need to be present every frame; it can be applied at any
submultiple of the frame rate (e.g., once every ESF superframe for DS1).
2
The input timings are all similar: RXDATI and RXSYI are sampled on the
In all framed, serial line formats, the content of the framing bit positions is
3
Channel 24
4
5
Conexant
6
7
8
ATM Transmitter/Receiver with UTOPIA Interface
F
S
(Figure
2
2-11). The timing on this
3
4
Channel 1
5
6
7
100046D
CN8223