cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 80

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.8 FEAC Channel and HDLC Data Link Programming
2-46
2.8.3.1 Sending a
Message
functions provided by the data link transmitter circuitry are transparency zero
stuffing, Frame Check Sequence (FCS) generation, idle flag generation, and abort
flag generation. There are no restrictions on the total length of the message.
Q.921 requires that all messages be an integral number of 8-bit bytes. The
transmitter can only transmit 8-bit bytes. The byte transmission times for the
transmitter are approximately those shown in
Table 2-28. Byte Transmission Times for Transmitter
data link channel to minimize processor interruptions. This buffer is located at
addresses 0x5C through 0x5F. Byte 0 is the least significant byte of 0x5C, byte 1
is the most significant byte of 0x5C, byte 2 is the least significant byte of 0x5D,
etc. Filling of this buffer is accomplished by the processor in the same manner as
writing to control registers. This buffer can be read as well as written to verify
contents. The buffer is divided into two halves to reduce the real-time
requirements on the processor. The processor loads four bytes (2 words) at a time,
while the data link transmitter reads from the other half of the buffer. This gives
the processor at least 160 s (at the fastest byte rate) to assemble the next four
bytes of message for transmission before the next interrupt is issued. Interrupts
are issued each time the transmitter circuitry reaches a 4-byte buffer boundary.
6–0 written to zero. This enables the transmitter to send idle flags on the data link.
No interrupts are generated when the data link is sending idle flags, thus no
processor intervention is required until a message is to be sent.
Beginning with an idle channel, the processor writes the first four bytes of
message data to the TX_DL_BUFFER. The first two bytes of data to be
transmitted should be written to 0x5C. The message is written to the buffer in
ascending order starting at 0x5C and ending at 0x5F. The least significant bit
(LSB) in each byte is transmitted first. This buffer can be written well before the
message is to be sent, if desired. After the first block of data is present in the
buffer memory, the processor writes to the DL_CTRL_STAT register to begin
transmission:
DS3 C bit Parity
G.751 E3
G.832 E3, E4
STS-1
STS-3c/STM-1
The transmitter implements an HDLC data link per ITU standard Q.921. The
An 8-byte buffer (organized as four 16-bit words) is provided for the transmit
The transmitter should be initialized with the DL_CTRL_STAT register bits
• Send Message = 1
• TxBytes[2:0] = 3
• Send FCS = 0
• Abort Message = 0
Mode
Conexant
ATM Transmitter/Receiver with UTOPIA Interface
284 s
357 s
125 s
125 s
42 s
Table
Byte Transmission Times
2-28.
100046D
CN8223