SST89E554 SST [Silicon Storage Technology, Inc], SST89E554 Datasheet
SST89E554
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SST89E554 Summary of contents
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 SST89E/V564 SST89E/VE554 FlashFlex51 MCU FEATURES: • 8-bit 8051 Family Compatible Microcontroller (MCU) with Embedded SuperFlash Memory • SST89E564/SST89E554 is 5V Operation – MHz Operation at 5V • SST89V564/SST89V554 is 3V Operation – MHz Operation at 3V • Fully Software and Development Toolset ...
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... IAP Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.4 In-Application Programming Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.5 Polling 4.2.6 Interrupt Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.0 TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.0 SERIAL I 6.1 Enhanced Universal Aysnchronous Receiver/Transmitter (UART 6.1.1 Framing Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Serial Peripheral Interface (SPI ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 2 FlashFlex51 MCU Preliminary Specifications S71181-03-000 9/01 384 ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 Hard Lock 8.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 Power-On Reset 9.2 Software Reset 9.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.4 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.5 Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.3 Standby Mode (Stop Clock ...
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... FIGURE 3-2: Program Memory Organization for SST89E554 and SST89V554 . . . . . . . . . . . . . . . . . . . . . 11 FIGURE 4-1: I/O Pin Assignments for External Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIGURE 4-2: Read- FIGURE 4-3: Select-Block1 / Select-Block0 FIGURE 4-4: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FIGURE 4-5: Block-Erase for SST89E564/SST89V564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FIGURE 4-6: Block-Erase for SST89E554/SST89V554 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIGURE 4-7: Sector-Erase FIGURE 4-8: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 4-9: Prog-SB1 / Prog-SB2 / Prog-SB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 4-10: Prog-SC0 / Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 4-11: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 6-1: SPI Master-slave Interconnection ...
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... TABLE 3-7: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-8: Timer/Counters SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-9: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 4-1: External Host Mode Commands for SST89E564/SST89V564 TABLE 4-2: External Host Mode Commands for SST89E554/SST89V554 TABLE 4-3: Signature Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 4-4: IAP Address Resolution for SST89E564/SST89V564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TABLE 4-5: In-Application Programming Mode Commands for SST89E564/SST89V564 . . . . . . . . . . . . 35 TABLE 4-6: In-Application Programming Mode Commands for SST89E554/SST89V554 . . . . . . . . . . . . 35 TABLE 4-7: Flash Memory Programming/Verification Parameters ...
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... LOCK IAGRAM Watchdog Timer SuperFlash EEPROM Primary Block 32K/64K x8 Secondary Block 8K x8 Timer 0 (16-bits) Timer 1 (16-bits) Timer 2 (16-bits) ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 Interrupt Control 8051 CPU Core 1 RAM 1K x8 I/O Port 0 I/O Port 1 Security Lock I/O Port 2 I/O Port 3 SPI ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 2.0 PIN ASSIGNMENTS 40 (T2) P1 (T2 Ex (SS#) P1 (MOSI) P1 (MISO) P1.6 7 40-pin PDIP 33 (SCK) P1.7 8 Top View 32 RST 9 31 (RXD) P3 (TXD) P3 (INT0#) P3 (INT1#) P3 (T0) P3 (T1) P3 (WR#) P3 (RD#) P3 ...
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... A forced high-to-low input transition on the PSEN# pin while the RST input is continually held high for more than ten machine cycles will cause the device to enter External Host mode for programming. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 ( ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 2- ESCRIPTIONS 1 Symbol Type Name and Functions RST I Reset: While the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition while the RST input pin is held high, the device will enter the External Host mode, otherwise the device will enter the Normal operation mode ...
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... P M ROGRAM EMORY ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 Bank Selection. Please refer to Figure 3-1 and Figure 3-2 for the program memory configurations. Program Bank Select is described in the next section. The 64K/32K x8 primary SuperFlash block is organized as 512/256 sectors, each sector consists of 128 Bytes. ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications EA FFFFH FFFFH E000H DFFFH External 8000H 64 KByte 7FFFH 2000H 1FFFH 0000H 0000H FIGURE 3- ROGRAM EMORY 3.2 Program Memory Block Switching The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block used for the lowest 8 KByte of the program address space ...
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... SC1 only applies to SST89E554 and SST89V554. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 ROGRAM EMORY LOCK WITCHING FOR 3.3 Data Memory The device has 1024 x 8 bits of on-chip RAM and can address KByte of external data memory ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 3- SFR M LASH LEX 1 F8H IPA 1 F0H B 1 E8H IEA 1 E0H ACC D8H 1 D0H PSW 1 C8H T2CON T2MOD 1 C0H WDTC 1 B8H IP SADEN 1 B0H P3 SFCF 1 A8H IE SADDR 1 A0H P2 1 98H SCON SBUF 1 90H ...
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... SFCM SuperFlash B2H Command SFDT SuperFlash B5H Data SFAL SuperFlash B3H Address Low SFAH SuperFlash B4H Address High ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 S Bit Address, Symbol, or Alternative Port Function MSB ACC[7:0] B[7: RS1 SP[7:0] DPL[7:0] DPH[7: ET2 ES0 ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 3- ATCHDOG IMER Direct Symbol Description Address 1 WDTC Watchdog Timer C0H Control WDTD Watchdog Timer 85H Data/Reload 1. Bit Addressable SFRs TABLE 3- SFR IMER OUNTERS Direct Symbol Description Address TMOD Timer/Counter Mode Control ...
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... P1 Port 1 90H 1 P2 Port 2 A0H 1 P3 Port 3 B0H 1. Bit Addressable SFRs ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 Bit Address, Symbol, or Alternative Port Function MSB SBUF[7:0] SM0/FE SM1 SM2 REN TB8 SADDR#[7:0] SADEN#[7:0] SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications SuperFlash Status Register (SFST) (Read Only Register) Location 7 6 0B6H SECD1 SECD2 Symbol Function SECD1 Security bit 1. SECD2 Security bit 2. SECD3 Security bit 3. Please refer to Table 4-6 for security lock options. FLASH_BUSYFlash operation completion polling bit. ...
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... E8H - - Symbol Function EBO Brown-out Interrupt Enable Enable the interrupt 0 = Disable the interrupt ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 SuperFlash Data Register SuperFlash Low Order Byte Address Register SuperFlash High Order Byte Address Register ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Interrupt Priority (IP) Location 7 6 B8H - - Symbol Function PT2 Timer 2 interrupt priority bit. PS Serial Port interrupt priority bit. PT1 Timer 1 interrupt priority bit. PX1 External interrupt 1 priority bit. PT0 Timer 0 interrupt priority bit. PX0 External interrupt 0 priority bit ...
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... Hardware sets the flag on watchdog overflow. WDT Watchdog timer refresh. 0: Hardware resets the bit when refresh is done. 1: Software sets the bit to force a watchdog timer refresh. SWDT Start watchdog timer. 0: Stop WDT. 1: Start WDT. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Watchdog Timer Data/Reload Register (WDTD) Location 7 6 085H Symbol Function WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set. SPI Control Register (SPCR) Location 7 6 D5H SPIE SPE Symbol ...
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... General-purpose flag bit. GF0 General-purpose flag bit. PD Power-down bit. 0: Power-down mode is not activated. 1: Activates Power-down mode. IDL Idle mode bit. 0: Idle mode is not activated. 1: Activates Idle mode. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 SPD5 SPD4 ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Serial Port Control Register (SCON) Location 7 6 SM1 98H SM0/FE Symbol Function FE Set SMOD0 = 1 to access FE bit framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software. ...
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... Address high order byte Data Input Data Output ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 logic high to a logic low while RST input is being held con- tinuously high. The device will stay in External Host Mode as long as RST = 1 and PSEN ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 4- XTERNAL OST Operation RST PSEN# Read- IH1 IL Chip-Erase V V IH1 IL Block-Erase V V IH1 IL Sector-Erase V V IH1 IL Byte-Program V V IH1 IL Byte-Verify (Read IH1 IL Prog-SC0 V V IH1 IL Prog-SC1 V V IH1 IL Prog-SB1 ...
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... Program commands, which are synchronized internally. The Read commands are asynchronous reads, indepen- dent of the PROG# signal level. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 Following is a detailed description of the External Host Mode commands: The Select-Block0 command enables Block pro- grammed in External Host Mode ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications The Byte-Verify command allows the user to verify that the device correctly performed an Erase or Program com- mand. This command will be disabled if any security locks are enabled. See Figure 4-11 for timing waveforms. The Prog-SB1, Prog-SB2, Prog-SB3 commands program the security bits, the functions of these bits are described in the Security Lock section and also in Table 8-1 ...
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... S -B ELECT LOCK Enables the selection of either of the flash memory blocks prior to issuing a Byte-Verify, Block-Erase, Sector- Erase, or Byte-Program. These commands apply to SST89E564/SST89V564 only. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 0000b 0030H BFH 92H for SST89V564 ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications T SU RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] FIGURE 4- HIP RASE Erases both flash memory blocks. Security lock is ignored and the security bits are erased too RST PSEN# ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] FIGURE 4- LOCK RASE FOR Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. ...
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... ALE/PROG# EA# P3[3] P3[7:6], P2[7:6] P3[5:4], P2[5:0] P1 FIGURE 4- ECTOR RASE Erases the addressed sector if the security lock is not activated on that flash memory block. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 ADS T PROG SST89E554/SST89V554 ADS T PROG 30 FlashFlex51 MCU Preliminary Specifications ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications RST PSEN# ALE/PROG# EA# P3[3] P3[5:4], P2[5: P3[7:6], P2[7:6] FIGURE 4- YTE ROGRAM Programs the addressed code byte if the byte location has been successfully erased and not yet programmed. Byte-Program operation is only allowed when the security lock is not activated on that flash memory block. ...
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... P0 P1 P3[5:4], P2[5:0] FIGURE 4-11 YTE ERIFY Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 ADS T PROG -SC1 1100b T AHA DO ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 4.2 In-Application Programming Mode The device offers either KByte of In-Application Programmable flash memory. During In-Application Pro- gramming, the CPU of the microcontroller enters IAP Mode. The two blocks of flash memory allow the CPU to execute user code from one block, while the other is being erased or reprogrammed concurrently ...
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... The Prog-SC0 command should reside only in Block 1. . ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 Prog-SC1 command is used to program the SC1 bit. This command only changes the SC1 bit and has no effect on BSEL bit until after a reset cycle. ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 4- PPLICATION ROGRAMMING Operation SFCM [6:0] 3 Block-Erase 3 Sector-Erase 3 Byte-Program 3 Byte-Verify (Read) 9 Prog-SB1 9 Prog-SB2 9 Prog-SB3 9 Prog-SC0 1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands. 2. Interrupt/Polling enable for flash operation completion SFCM[7] =1: Interrupt enable for flash operation completion 0: polling enable for flash operation completion 3 ...
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... The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is initiated by any instruction ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 /V P ERIFICATION ARAMETERS ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications AAR is only available when using the serial port in either mode Setting the SM2 bit in SCON enables AAR. Each slave must have its SM2 bit set when waiting for an address (9th bit = 1). The Receive Interrupt (RI) flag will only be set when the received byte matches either the Given or Broadcast Address ...
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... SCK (CPOL=0) SCK (CPOL=1) MOSI MSB (from Master) MISO MSB * (from Slave) SS# (to Slave) * Not defined but normally LSB of previously transmitted character FIGURE 6-3: SPI T RANSFER ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 CPHA = 0 ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 7.0 WATCHDOG TIMER The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and auto- matic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period ...
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... OCK Notes Programmed (Cell logic state = 0 Unprogrammed (Cell logic state = 1 Not Locked Hard Locked SoftLocked. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 mand mailbox register, SFCM, executed from a Locked (Hard Locked or SoftLocked) block, can be operated on a SoftLocked block: Block-Erase, Sector-Erase, Byte-Pro- gram and Byte-Verify ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 8- ECURITY OCK PTIONS Security Lock Bits Level SFST[7:5] SB1 1 000 U 2 100 P 3 011 U 101 P 010 U 110 P 001 U 4 111 Programmed (Cell logic state = 0 Unprogrammed (Cell logic state = 1). ...
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... Location of MOVC instruction 2. External Host Byte-Verify access does not depend on a source address. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 T ABLE External Host Source Target Byte-Verify 1 Address Address Allowed ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 9.0 RESET A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable ...
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... PCON register. In the Power Down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. To retain the on-chip RAM and all of the spe- cial function registers’ values, the minimum V ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 S EQUENCE Vector Interrupt ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 9- OWER AVING ODES Mode Initiated by Idle Mode Software (Set IDL bit in PCON) Power Down Software Mode (Set PD bit in PCON) Standby (Stop External hardware gates OFF Clock) Mode the external clock input to the MCU ...
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... FIGURE 9- SCILLATOR HARACTERISTICS ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 9.7 Recommended Capacitor Values for Crystal Oscillator Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one applica- tion to another. C1 and C2 should be adjusted appropri- ately for each design. The table below, shows the typical values for C1 and given frequency ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 10.0 ELECTRICAL SPECIFICATION Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
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... Power Supply Current DD In-Application Mode @ 20 MHz @ 40 MHz Active Mode @ 20 MHz @ 40 MHz Idle Mode @ 20 MHz @ 40 MHz Standby (Stop Clock) Mode Power Down Mode ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 -40°C +85°C, 40MH DEVICES Test Conditions 4.5 < V < 5.5 DD 4.5 < V < 5.5 DD 4.5 < V < ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 10- LECTRICAL HARACTERISTICS T = 0°C +70°C TO amb Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Input High Voltage (XTAL1, RST) IH1 V Output Low Voltage (Ports 1.5, 1.6, 1. Output Low Voltage (Ports ...
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... All other pins disconnected FIGURE 10- EST ONDITION DLE ODE ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 on ALE and PSEN# to momentarily fall below the V OH for Power Down is 2.0V 384 ILL F26.2 All other pins disconnected FIGURE 10- ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 10.4 AC Electrical Characteristics AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 10- LECTRICAL HARACTERISTICS T = 0°C +70°C TO amb Symbol Parameter 1/T Oscillator Frequency ...
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... AC Inputs during testing are driven at V IHT (V DD -0.5V) for Logic "1" and V ILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are (0. 0.9) and V LT (0. 0.1) FIGURE 10- ESTING NPUT ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 ( ONTINUED OF -40°C +85° ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications T LHLL ALE T AVLL PSEN# PORT 0 PORT 2 FIGURE 10- XTERNAL ROGRAM T LHLL ALE PSEN# RD# T AVLL A7-A0 FROM RI or DPL PORT 0 PORT 2 FIGURE 10- XTERNAL ATA ©2001 Silicon Storage Technology, Inc. T LLIV T LLPL T PLIV T PLAZ ...
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... Low Time CLCX T Rise Time CLCH T Fall Time CHCL -0 -0.1 0.45 V FIGURE 10- XTERNAL LOCK ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 T WLWH T LLWL T LLAX T QVWX T QVWH DATA OUT T AVWL P2[7:0] or A15-A8 FROM DPH EMORY RITE YCLE RIVE Oscillator ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 10- ERIAL ORT IMING Symbol Parameter T Serial Port Clock Cycle Time XLXL T Output Data Setup to Clock Rising Edge QVXH T Output Data Hold After Clock Rising Edge XHQX T Input Data Hold After Clock Rising Edge ...
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... SST89V554-25-I-PI SST89V554-25-I-NJ Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 Suffix2 Package Modifier ...
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... FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 12.0 PACKAGING DIAGRAMS 40 1 Pin #1 Identifier .065 .075 Base Plane Seating Plane .015 Min. .063 .090 Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .115; SST min is less stringent 2 ...
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... HIN UAD LAT ACK SST TQJ ACKAGE ODE Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2001 Silicon Storage Technology, Inc. SST89E564 / SST89V564 / SST89E554 / SST89V554 34 33 .30 .45 10.00 BSC 12.00 .80 BSC BSC 23 .09 22 ...