SST89E554 SST [Silicon Storage Technology, Inc], SST89E554 Datasheet - Page 8

• Manufacturer Part Number: SST89E554
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

2.1 Pin Descriptions
TABLE
©2001 Silicon Storage Technology, Inc.
Symbol
PSEN#
P0[7:0]
P1[7:0]
P2[7:0]
P3[7:0]
P1[0]
P1[1]
P1[4]
P1[5]
P1[6]
P1[7]
P3[0]
P3[1]
P3[2]
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]
2-1: P
I/O with internal
I/O with internal
I/O with internal
IN
pull-ups
pull-ups
pull-ups
Type
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
ESCRIPTIONS
1
Name and Functions
Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can
sink several LS TTL inputs. Port 0 pins float that have “1”s written to them, and in this state
can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this application, it uses strong internal pull-
ups when transitioning to V
mode programming, and outputs the code bytes during the external host mode verification.
External pull-ups are required during program verification.
Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when “1”s are
written to them and can be used as inputs in this state. As inputs, Port 1 pins that are exter-
nally pulled low will source current (I
ups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address
bytes during the external host mode programming and verification.
T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2
T2EX: Timer/Counter 2 capture/reload trigger and direction control
SS#: Master Input or Slave Output for SPI
MOSI: Master Output line, Slave Input line for SPI
MISO: Master Input line, Slave Output line for SPI
SCK: Master clock output, slave clock input line for SPI
Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled
high by the internal pull-ups when “1”s are written to them and can be used as inputs in this
state. As inputs, Port 2 pins that are externally pulled low will source current (I
10-3 and 10-4) because of the internal pull-ups. Port 2 sends the high-order address byte
during fetches from external Program memory and during accesses to external Data Memory
that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups
when transitioning to V
order address bits during the external host mode programming and verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when “1”s are
written to them and can be used as inputs in this state. As inputs, Port 3 pins that are exter-
nally pulled low will source current (I
ups. Port 3 also receives some control signals and a partial of high-order address bits during
the external host mode programming and verification.
RXD: Serial input line
TXD: Serial output line
INT0#: External Interrupt 0 Input
INT1#: External Interrupt 1 Input
T0: External count input to Timer/Counter 0
T1: External count input to Timer/Counter 1
WR#: External Data Memory Write strobe
RD#: External Data Memory Read strobe
Program Store Enable: PSEN# is the Read strobe to External Program Store. When the
device is executing from Internal Program Memory, PSEN# is inactive (V
device is executing code from External Program Memory, PSEN# is activated twice each
machine cycle, except when access to External Data Memory while one PSEN# activation is
skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while
the RST input is continually held high for more than ten machine cycles will cause the device
to enter External Host mode for programming.
(1
OF
2)
SST89E564 / SST89V564 / SST89E554 / SST89V554
OH
. Port 2 also receives some control signals and a partial of high-
OH
8
. Port 0 also receives the code bytes during the external host
IL
IL
, see Tables 10-3 and 10-4) because of the internal pull-
, see Tables 10-3 and 10-4) because of the internal pull-
Preliminary Specifications
FlashFlex51 MCU
OH
S71181-03-000 9/01
). When the
IL
, see Tables
384