SST89E554 SST [Silicon Storage Technology, Inc], SST89E554 Datasheet - Page 21

• Manufacturer Part Number: SST89E554
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

FlashFlex51 MCU
SST89E564 / SST89V564 / SST89E554 / SST89V554
Preliminary Specifications
Watchdog Timer Data/Reload Register (WDTD)
SPI Control Register (SPCR)
©2001 Silicon Storage Technology, Inc.
Location
Location
085H
D5H
Symbol
WDTD
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1, SPR0 SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured
SPIE
7
7
Function
Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set.
SPE
Function
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1[4], P1[5], P1[6], P1[7].
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
Clock Phase control bit.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK
and the oscillator frequency, f
6
6
SPR1
0
0
1
1
DORD
5
5
Watchdog Timer Data/Reload
SPR0
0
1
0
1
MSTR
4
4
SCK = f
OSC
21
CPOL
, is as follows:
3
3
OSC
128
16
64
4
divided by
CPHA
2
2
SPR1
1
1
SPR0
0
0
S71181-03-000 9/01
Reset Value
00000000b
Reset Value
00000100b
384