SST89E554 SST [Silicon Storage Technology, Inc], SST89E554 Datasheet - Page 36

• Manufacturer Part Number: SST89E554
• Description: FlashFlex51 MCU
• Manufacturer: SST [Silicon Storage Technology, Inc]

TABLE
5.0 TIMERS/COUNTERS
The device has three 16-bit registers that can be used as
either timers or event counters. The three Timers/Counters
are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2).
Each is designated a pair of 8-bit registers in the SFRs.
The pair consists of a most significant (high) byte and least
significant (low) byte. The respective registers are TL0,
TH0, TL1, TH1, TL2, and TH2.
6.0 SERIAL I/O
6.1 Enhanced Universal Aysnchronous
Receiver/Transmitter (UART)
The device Serial I/O port is a full duplex port that allows
data to be transmitted and received simultaneously in
hardware by the transmit and receive registers, respec-
tively, while the software is performing other tasks. The
transmit and receive registers are both located in the
Serial Data Buffer (SBUF) special function register. Writ-
ing to the SBUF register loads the transmit register, and
reading from the SBUF register obtains the contents of
the receive register.
The UART has four modes of operation which are selected
by the Serial Port Mode Specifier (SM0 and SM1) bits of
the Serial Port Control (SCON) special function register. In
all four modes, transmission is initiated by any instruction
©2001 Silicon Storage Technology, Inc.
Parameter
Reset Setup Time
Read-ID Command Width
PSEN# Setup Time
Address, Command, Data Setup Time
Chip-Erase Time
Block-Erase Time
Sector-Erase Time
Program Setup Time
Address, Command, Data Hold
Byte-Program Time
Select-Block Program Time
Security bit Program Time
Verify Command Delay Time
Verify High Order Address Delay Time
Verify Low Order Address Delay Time
1. Program and Erase times will scale inversely proportional to programming clock frequency.
2. All timing measurements are from the 50% of the input to 50% of the output.
3. Each byte must be erased before programming.
1,2
4-7: F
LASH
3
M
EMORY
P
ROGRAMMING
SST89E564 / SST89V564 / SST89E554 / SST89V554
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
PROG
ADS
AHA
/V
PSB
ALA
SU
RD
ES
CE
BE
SE
DH
PB
PS
OA
ERIFICATION
36
that uses the SBUF register as a destination register.
Reception is initiated in mode 0 when the Receive Interrupt
(RI) flag bit of the Serial Port Control (SCON) SFR is
cleared and the Reception Enable/ Disable (REN) bit of the
SCON register is set. Reception is initiated in the other
modes by the incoming start bit if the REN bit of the SCON
register is set.
6.1.1 Framing Error Detection
Framing Error Detection allows the serial port to auto-
matically check for valid stop bits in Modes 1, 2 or 3. If
a stop bit is missing the Framing Error bit (FE) will be
set. The software can then check this bit after a recep-
tion to detect communication errors. The FE bit must
be cleared by software.
The FE bit is located in SCON and shares the same bit
address as SM0. The SMOD0 bit located in the PCON reg-
ister determines which of these two bits is accessed. When
SMOD0 = 0, SCON[7] will act as SM0. When SMOD0 = 1,
SCON[7] will act as FE.
6.1.2 Automatic Address Recognition
Automatic Address Recognition (AAR) reduces the CPU
time required to service the serial port in a multiprocessor
environment. When using AAR, the serial port hardware
will only generate an interrupt when it receives its own
address, thus eliminating the software overhead required to
compare addresses.
P
ARAMETERS
1.125
Min
1.2
3
1
0
0
Max
125
500
100
30
50
80
50
50
50
Preliminary Specifications
FlashFlex51 MCU
S71181-03-000 9/01
Units
ms
ms
ms
µs
µs
µs
ns
µs
ns
µs
ns
µs
ns
ns
ns
T4-7.5 384
384