SST89E554 SST [Silicon Storage Technology, Inc], SST89E554 Datasheet - Page 27

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SST89E554

Manufacturer Part Number
SST89E554
Description
FlashFlex51 MCU
Manufacturer
SST [Silicon Storage Technology, Inc]
Datasheet

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FlashFlex51 MCU
SST89E564 / SST89V564 / SST89E554 / SST89V554
Preliminary Specifications
The Byte-Verify command allows the user to verify that the
device correctly performed an Erase or Program com-
mand. This command will be disabled if any security locks
are enabled. See Figure 4-11 for timing waveforms.
The Prog-SB1, Prog-SB2, Prog-SB3 commands program
the security bits, the functions of these bits are described in
the Security Lock section and also in Table 8-1. Once pro-
grammed, these bits can only be erased through a Chip-
Erase command. See Figure 4-9 for timing waveforms.
Prog-SC0 command programs SC0 bit, which determines
the state of SFCF[0] out of reset. Once programmed, SC0
can only be restored to an erased state via a Chip-Erase
command. See Figure 4-10 for timing waveforms.
Prog-SC1 command programs SC1 bit, which determines
the state of SFCF[1] out of reset. Once programmed, SC1
can only be restored to an erased state via a Chip-Erase
command. See Figure 4-10 for timing waveforms. Prog-
SC1 is for SST89E554/SST89V554 only.
4.1.4 External Host Mode Clock Source
In External Host Mode, an internal oscillator will provide
clocking for the device. The on-chip oscillator will be turned
on as the device enters External Host Mode; i.e. when
PSEN# goes low while RST is high. During External Host
Mode, the CPU core is held in reset. Upon exit from Exter-
nal Host Mode, the internal oscillator is turned off.
4.1.5 Flash Operation Status Detection Via External
Host Handshake
The device provides two methods for an external host to
detect the completion of a flash memory operation to opti-
mize the Program or Erase time. The end of a flash mem-
ory operation cycle can be detected by:
4.1.5.1 Ready/Busy# (P3[3])
The progress of the flash memory programming can be
monitored by the Ready/Busy# output signal. P3[3] is
driven low, some time after ALE/PROG# goes low during a
flash memory operation to indicate the Busy# status of the
Flash Control Unit (FCU). P3[3] is driven high when the
flash programming operation is completed to indicate the
Ready status.
©2001 Silicon Storage Technology, Inc.
1. monitoring the Ready/Busy# bit at P3[3];
2. monitoring the Data# Polling bit at P0[3].
27
4.1.5.2 Data# Polling (P0[3])
During a Program operation, any attempts to read (Byte-
Verify), while the device is busy, will receive the comple-
ment of the data of the last byte loaded (logic low, i.e. “0” for
an erase) on P0[3] with the rest of the bits “0”. During a Pro-
gram operation, the Byte-Verify command is reading the
data of the last byte loaded, not the data at the address
specified.
4.1.6 Step-by-step instructions to perform
External Host Mode commands
To program data into the memory array, apply power
supply voltage (V
form the following steps:
10. Verify the flash memory contents.
1. Maintain RST high and set PSEN# from logic high
2. Raise EA# High (V
3. Issue Read-ID command to enable the External
4. Verify that the memory blocks or sectors for pro-
5. Select the memory location using the address
6. Present the data in on P0[7:0].
7. Pulse ALE/PROG#, observing minimum pulse
8. Wait for low to high transition on READY/BUSY#
9. Repeat steps 5 - 8 until programming is finished.
to low, in sequence according to the appropriate
timing diagram.
Host Mode.
gramming is in the erased state, FFH. If they are
not erased, then erase them using the appropriate
Erase command.
lines (P3[5:4], P2[5:0], P1[7:0]).
width.
(P3[3]).
DD
) to V
IH
).
DD
and RST pins, and per-
S71181-03-000 9/01
384

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