vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 103

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
3.2.92 EBh: Master Interface Command (MIC)
The following table shows the bit assignments for the Master Interface Command register.
Register Name:
Address:
Reset Value:
Bit
7
6
5
4
3
2
Bit Label
SDAI
SDAO
SRST
GO
RW
ACK
MIC
EBh
1100_0000b
Access
R
R/W
R/W
R/W
R/W
R/W
Description
Serial Data Input
This read-only bit indicates the current state of the master serial interface SDA
input.
1: SDA signal is tri-stated and is being pulled HIGH by an external pull-up
resistor.
0: device (including the VSC055-01) is actively driving a low value onto the SDA wire.
After a reset or power on, this bit is unknown.
Serial Data Output
This bit provides low-level drive control of the master serial interface SDA
signal.
Setting this bit allows the automatic functions of this master serial interface to
control the SDA output value.
Clearing this bit forces a zero value onto the serial bus, regardless of the state
of the automatic controls. Under normal circumstances, this bit should always
be written to a 1. The read value for this bit returns the programmed wired-AND
output value being driven, not the live value on the serial bus.
After a reset or power on, this bit is set.
Soft Reset
Setting this bit performs a soft reset operation. The soft reset operation clears
all state machines and returns the master serial interface to an idle (non-
driving) state with regard to SCL and SDA. The soft reset is one clock in
duration.
This bit is self-clearing. After a reset or power on, this bit is cleared.
GO
Setting this bit initiates a byte transfer on the serial bus. This bit automatically
clears itself when the transfer is complete.
After a reset or power on, this bit is cleared.
Read/Write
This bit determines whether the immediate byte to be transferred is a read or a
write transaction.
If this bit is set, the transfer is a read.
If this bit is cleared, the transfer is a write.
After a reset or power on, this bit is cleared.
Serial Bus Acknowledge
This bit provides control for the acknowledge bit of a serial byte transfer.
Setting this bit for a read transaction causes the serial interface to drive the
ACK bit at the end of the transaction’s bit sequence. This must be used for all
but the last byte of sequential read operations.
Reading this bit after a write transaction has completed indicates whether or
not the targeted slave device acknowledged the byte transfer.
After a reset or power on, this bit is cleared.
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January 2008
Revision 4.1