vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 109

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

VSC055-01
Data Sheet
Bit
6:5
4:2
1
Bit Label
BYP1-0
FS2-0
DD
Access
R/W
R/W
R/W
Description
Bypass Select
These two bits determine the bypass function of the odd-numbered I/O pins
P0.7, P0.5, P0.3, and P0.1.
Setting either or both of these bits causes the I/O pin to be configured as an
output that reflects the input state of the corresponding even-numbered I/O pins
P0.6, P0.4, P0.2, and P0.0.
As an example, P0.1 can be configured as an output that follows the signal
applied to the P0.0 input. These two register bits only appear in the
odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For
the available output drive combinations, see
Note: These bits are only used when the bypass function is desired. They
should not be set when normal GPIO operation, PBC operation, or fan speed
monitoring are selected through the appropriate registers or through the use of
the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function
are the highest priority controls for the appropriate I/O pin. The next highest
priorities are the PBC function (Port 3 through Port 6) and fan speed monitoring
(Port 1 and Port 2). The lowest priorities are the bit control features found in the
GPD, DD, and BCP registers.
Only one mode of operation should be enabled for each I/O pin at any time. If a
mode change is desired, first disable the existing mode, then enable the new
mode.
Function Select
These three bits, along with the PTE, DD, and GPD bits, determine the function
of each I/O pin.
When configured as an output, the FS2-0 bits determine the rate at which the
high current drive I/O toggles, providing a simple mechanism for flashing LEDs.
The DD and GPD bits can be used to drive each I/O individually and to take the
place of the byte wide controls found in the DD and GPD registers. Note that
the DD bit is always de-asserted to configure the I/O as an output. Asserting
the DD bit tri-states the I/O and effectively configures the I/O as an input. The
six bits allow the user to select one of seven flash rates or eight user-
programmable pulse trains, as well as to drive the LED both on and off. The
output can be enabled to drive in an open-source (output drives to V
external pull-down resistor) or open-drain (output drives to V
pull-up) configuration when using the flashing mechanism. For available
combinations to drive an LED, see
When configured as an input, the DD bit is asserted. These bits determine the
type of I/O pin edge transition that generates an interrupt condition. Transition
detectors within the device filter the changes observed at the I/O pin and
determine if a valid transition has occurred. If a valid transition occurs, the INT#
pin asserts and a binary value equal to the address of this register appears in
the BCIS register. For available input edge combinations, see
Note: When configuring an I/O pin from an output to an input with interrupt
enabled, it is recommended that the data direction change and interrupt
enabling be accomplished with separate register write operations. This
guarantees that any I/O transition that occurs as a result of the data direction
change, which may rely on the weak internal pull-up resistor, does not generate
an unexpected interrupt.
Data Direction
This bit determines the direction of the data flow through the I/O pin.
To enable the respective I/O pin as an input, set the appropriate bit.
To enable the respective I/O pin as an output, reset the appropriate bit.
Each I/O pin can be individually configured as a true bidirectional function. To
implement an open-drain or open-source function, set or reset the appropriate
data bit using the data direction bit as the programmed data value.
After a reset or power on, these bits are set to a binary 1, enabling the I/O as an
input with weak pull-up.
109 of 133
Table 5,
page 80.
Table 4,
page 80.
SS
Table 6,
with an external
January 2008
Revision 4.1
DD
page 81.
with an