vsc055xkm-01 Maxim Integrated Products, Inc., vsc055xkm-01 Datasheet - Page 112

• Manufacturer Part Number: vsc055xkm-01
• Description: Enhanced I?c Backplane Controller
• Manufacturer: Maxim Integrated Products, Inc.

Revision 4.1
January 2008
Bit
6
5:4
3:0
Bit Label
COD
PDS1-0
SP3-0
Access
R/W
R/W
Description
CKOUT Output Disable
This bit enables or disables the CKOUT pin.
If this bit is set, the CKOUT pin stops toggling with the output set to a logic 1.
If this bit is reset, the CKOUT pin reflects the input clock rate when CKSEL2 is
LOW and reflects a divided clock rate when CKSEL2 is HIGH. The default
state of this bit is LOW, which enables normal operation.
This bit is cleared when a soft reset operation occurs, re-enabling the CKOUT
pin if it was previously disabled through a write to this register bit.
Pulse-Width Modulation Divider Select
These two bits determine the divider that is used for the pulse-width
modulation circuits. The base frequency range of all pulse-width modulation
circuits are controlled by these bits. Each pulse-width modulation circuit can be
programmed to select one of the three available frequencies within the range.
After a reset or power on, these register bits are cleared to a 0. The available
frequency ranges are as follows:
Synchronization Period
These four bits determine the synchronization period of the device. The
synchronization function can be used by a single VSC055-01 device for
internal synchronization or by multiple VSC055-01devices for chip-to-chip
synchronization.
At the end of the synchronization period, a pulse is generated on the SYNC#
pin that causes this device, as well as all other devices attached to the SYNC#
pin, to re-synchronize their internal dividers. The device that asserts the
SYNC# pin first determines the base synchronization period and effectively
controls all other devices. The synchronization period can vary from 2 seconds
(0001b) to 16 seconds (1111b), depending on the value in these four bits. The
user must ensure that all devices use the same synchronization period and
that the period selected is a multiple of all selected LED flash rate periods,
including the pulse train values.
These four bits are enabled when the SYNCEN pin is tied to V
non-zero to enable device synchronization. Additionally, an external pull-up
resistor (10 kΩ) must be connected to the SYNC# pin.
PDS1
0
0
1
1
112 of 133
PDS0
0
1
0
1
Pulse-Width Modulation Frequency Range
26 kHz, 52 kHz or 104 kHz (divide-by-3)
5.2 kHz, 10.4 kHz or 20.8 kHz (divide-by-15)
1.04 kHz, 2.08 kHz or 4.16 kHz (divide-by-75)
208Hz, 416Hz, 833Hz (divide-by-375)
DD
VSC055-01
Data Sheet
and must be