ST20-C1 STMICROELECTRONICS [STMicroelectronics], ST20-C1 Datasheet - Page 144
ST20-C1
Manufacturer Part Number
ST20-C1
Description
Instruction Set Reference Manual
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST20-C1.pdf
(205 pages)
- Current page: 144 of 205
- Download datasheet (842Kb)
smacloop
Code: 21 F6
Description: Multiply pairs of signed16-bit values and accumulate the products. On
entry Areg and Breg contain the addresses of arrays X and Y of 16-bit values and
Creg holds the initial 32-bit accumulator. On exit the accumulator is in Areg, while
Breg and Creg contain the next addresses in the X and Y arrays respectively. The X
values can be in a circular buffer whose address is exactly divisible by the size. The
loop count, buffer size, mode and scaling codes, held in the status register, may be set
by the smacinit instruction.
Warning: This instruction is not interruptible. If interrupt latency is critical then a
similar result may be achieved by executing the instruction many times with small
counts. The result may not be the same, since rounding occurs at the end of the
instruction from the internal 48-bit accumulator to a 32-bit result.
Definition:
144/205
if (Status
else if (Status
else if ( overflow )
{
}
else if ( underflow )
{
}
else
{
}
Breg
Creg
where
Areg
Areg
Status
Areg
Status
Areg
Areg
acc = (Creg << shift1) + (1 << (shift1-1))
if (Status
overflow
overflow
underflo w
xaddress (Status
Breg + (2
+
mac_count
max
underflo w
min
max
min
acc >>
)
i=0..n-1
– the value of acc is calculated to 48-bit precision
set
arith
set
[sixteen[xaddress(i )]
= 0) n=256
)
Status
shift1
mac_count
mac_count
short multiply accumulate loop
)
)
(sixteen[Breg + 2.i] << shift2)]
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