ST20-C1 STMICROELECTRONICS [STMicroelectronics], ST20-C1 Datasheet - Page 75

• Manufacturer Part Number: ST20-C1
• Description: Instruction Set Reference Manual
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

occurred then this is the only way that the nested interrupts can identify the state of
the user process.
If the exception is a schedule_exception trap then the trap handler also needs to
know the process due to be scheduled. The descriptor of the process (as held in the
exception vector table) is saved at SavedTaskDescriptor near the bottom of the
address space.
6.5
Exception handlers cannot be queued, so they must not deschedule. This means that
the following are not permitted inside exception handlers:
Exception handlers may be nested to arbitrary depth, but they are not re-entrant, so
care should be taken to ensure that the exception which caused the handler to run
cannot occur while the handler is running, trapped or interrupted.
6.6
All interrupts, whether from on-chip peripherals or external pins, are routed through an
interrupt controller, which is normally an on-chip peripheral. The interrupt controller is
responsible for arbitration between multiple interrupt signals. The design of the
interrupt controller varies between ST20 variants. Typically, interrupt priorities are
managed by the interrupt controller, which will usually track the priority of the highest
level task currently executed by the core, and will interrupt the ST20-C1 again if a
higher priority interrupt occurs.
When an interrupt is requested by the interrupt controller, the ST20-C1 always
changes context to the appropriate interrupt handler. An interrupt request is accompa-
nied by an identifier for the interrupt handler, which is the exception level. The ST20-
C1 scheduler uses the exception level from the interrupt controller to start the appro-
priate interrupt handler.
The CPU also sets the interrupt_mode bit in the status register and clears the
trap_mode and user_mode bits. The interrupt_mode bit indicates that an interrupt
handler is running, though it may have been trapped.
When the interrupt handler executes the eret instruction, the CPU signals to the
interrupt controller that the handler has returned. This allows the interrupt controller to
keep track of which interrupt handlers are running, so that it can start a low priority
waiting interrupt when a higher priority handler completes.
If the interrupt controller requests an interrupt level which has a null interrupt handler
then the CPU signals to the controller that the interrupt has completed.
Restrictions on exception handlers
the stop instruction;
the timeslice instruction.
Interrupts
6 Exceptions
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