ST20-C1 STMICROELECTRONICS [STMicroelectronics], ST20-C1 Datasheet - Page 53

• Manufacturer Part Number: ST20-C1
• Description: Instruction Set Reference Manual
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Any bit may be read from the IO register by:
The IO register is global and is not changed or saved by a context switch. If more than
one process accesses the IO register then it may need to be protected by a sema-
phore. On reset the IO register is set to all zeros.
4.11.2 Memory-mapped peripherals
On-chip peripherals may have memory-mapped registers in the address space .
Access to these registers is performed in the same way as accessing memory. If a
peripheral has a block of word-aligned registers with base address peripheral then a
register with word offset register may be read by:
and value may be written to the register by:
4.11.3 Channel-type peripherals
Some peripherals, for example peripherals using DMA (direct memory access), may
use a channel-type control model. This section describes how to use such periph-
erals, which use a micro-interrupt to notify the CPU that an assigned job is completed.
This type of peripheral works best with a multi-tasking program, so that the CPU has
other processes to execute while the peripheral is busy. However, if multi-tasking is not
otherwise required, then an interrupt model can be used. Multi-tasking is described in
Chapter 7 and interrupts and the exception vector table are described in Chapter 6.
Multi-tasking
The principle of using the channel model with multi-tasking is that the CPU tells the
peripheral to start a job and then deschedules the current process. The job might be
peripheral input/output or DMA transfer. This allows the CPU to continue executing
other processes while the job is in progress. When the peripheral completes the job it
signals to the CPU, which reschedules the process.
To enable this to happen, the task descriptor of a user process can be entered into the
exception vector table. This entry is called the peripheral channel. The peripheral
signals a micro-interrupt, which interrupts the CPU with the exception level associated
with the user process. The CPU recognizes that the exception vector table entry is a
user process because bit zero is UserProcessType , and either adds the process to the
end of the scheduling queue or takes a schedule exception trap if installed. The
scheduling exception trap allows a scheduling kernel to control the rescheduling of the
process.
In more detail, the steps to perform a job using this model are:
ldc 0; dup; io;
ld peripheral;
ldnl register;
ld value;
ld peripheral;
stnl register;
ldc bit_number; bitld;
4 Using ST20-C1 instructions
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