ST20-C1 STMICROELECTRONICS [STMicroelectronics], ST20-C1 Datasheet - Page 72

• Manufacturer Part Number: ST20-C1
• Description: Instruction Set Reference Manual
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

6.2 Exception vector table
Scheduling and timeslices are discussed in Chapter 7. Using user processes as
exceptions to handle peripherals is described in section 4.11.
6.2
The exception vector table maps each exception level to a user process or exception.
The base of the exception vector table is at the fixed address ExceptionBase
(#80000040) in on-chip memory, and the exception level is the word offset from the
ExceptionBase to the vector. Thus the exception level is used as an index into the
exception vector table.
The address of the user process or exception is always word aligned, and so has bits
0 and 1 set to zero. The entry in the exception vector table is a descriptor , which
consists of the address of the user process or exception ORed with a type. The type is
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el_illegal_instr_trap
This trap is taken when the CPU encounters an instruction with an illegal op-
code. If the trap is null then the instruction is treated as a nop .
el_idle_trap
This trap is taken when the CPU becomes idle, i.e. the current process exe-
cutes a stop when there are no active processes waiting for CPU time, or a
timeslice is trapped or interrupted so that there are no active processes waiting
when the CPU attempts to start the next process. If the trap is null then the
CPU waits for an interrupt or for a process to be scheduled. This trap is used
by software scheduling kernels.
el_schedule_exception_trap
This trap is taken when an interrupt is received from a peripheral and the
exception level is assigned to a user process, which will generally be desched-
uled waiting for the peripheral to complete a job. If the trap is null then the user
process is queued. This trap is used by software scheduling kernels.
el_run_trap
This trap is taken when the run instruction is executed. If the trap is null then
the CPU adds the process to the back of the scheduling queue. This trap is
used by software scheduling kernels.
el_stop_trap
This trap is taken when the stop instruction is executed. If the trap is null then
the current process is descheduled and the CPU starts executing the process
on the front of the scheduling queue, or goes idle if there is none. This trap is
used by software scheduling kernels.
el_timeslice_trap
This trap is taken when a timeslice is due and enabled and the timeslice
instruction is executed. If the trap is null then the current process is timesliced,
i.e. placed on the back of the scheduling queue. This trap is used by software
scheduling kernels.
Exception vector table