ST20-C1 STMICROELECTRONICS [STMicroelectronics], ST20-C1 Datasheet - Page 37
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ST20-C1
Manufacturer Part Number
ST20-C1
Description
Instruction Set Reference Manual
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST20-C1.pdf
(205 pages)
- Current page: 37 of 205
- Download datasheet (842Kb)
Each divstep generates four bits of the unsigned quotient, so eight divstep s are
needed for a full 32-bit unsigned division, and will also generate a remainder. The
result of the division is the integer division rounded towards zero (truncated). The
quotient is left in Breg, and the remainder in Creg, so a rotation pops the quotient into
the Areg.
unsign is used to separate the sign from the magnitude of the operands before
performing the division. Division is then performed on the magnitudes, and the signs
of the results may be derived from the signs of the operands.
Overflow can occur only if the divisor (Areg) is zero, or if the dividend (Breg) is
MostNeg and the divisor is -1. divstep does not detect these cases, and does not set
any status bits, so a check should be applied before performing the division.
The following code sequence performs the integer division a/b . The signed quotient is
left in Areg.
The following code sequence performs the remainder a rem b . The signed remainder
is left in Areg.
4.4.3
In saturated arithmetic, when an overflow or underflow occurs the result is set to the
most positive or most negative possible result respectively, instead of the least signifi-
cant bits of the full result. This ensures that the result is as near as possible to the real
value and prevents glitches caused by wrap-around.
POS:
END:
POS:
END:
Saturated arithmetic
ldc 0; rot;
rot;
rot;
a; b; ldc 0; arot; unsign;
arot; unsign; cj POS;
divstep; divstep; divstep; divstep;
divstep; divstep; divstep; divstep;
rot; not; adc 1;
j END;
divstep; divstep; divstep; divstep;
divstep; divstep; divstep; divstep;
rot;
a; b; ldc 0; rev; unsign;
eqc 2; arot; unsign; cj POS;
divstep; divstep; divstep; divstep;
divstep; divstep; divstep; divstep;
arot; not; adc 1;
j END;
divstep; divstep; divstep; divstep;
divstep; divstep; divstep; divstep;
arot;
4 Using ST20-C1 instructions
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