ST20-C1 STMICROELECTRONICS [STMicroelectronics], ST20-C1 Datasheet - Page 193
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ST20-C1
Manufacturer Part Number
ST20-C1
Description
Instruction Set Reference Manual
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST20-C1.pdf
(205 pages)
- Current page: 193 of 205
- Download datasheet (842Kb)
Scheduling kernel
Scheduling queue
Secondary instruction
Semaphore
Set
Sign extension
Sign bit
Signed value
Sleep
Slot
Stack
Stack, evaluation
State
Status register
Code to override the ST20 built-in microcode scheduler , consisting mainly of trap
handlers which are taken when a scheduling event occurs.
The queue of processes waiting for CPU time.
An instruction encoded using an operate instruction component. A secondary
instruction has no data part associated with it, as the instruction data value is used
to identify the instruction. cf. primary instruction .
A mechanism for synchronizing and signalling between processes.
A bit is set when its value is 1.
A signed value can be extended to occupy more bits by filling the most significant
bits with copies of the sign bit.
The most significant bit of a signed value , used to indicate the sign of the value.
Value which could be positive or negative depending on the sign bit .
The CPU is asleep when its clocks are turned off to reduce power consumption.
The CPU automatically goes to sleep after it becomes idle. It is woken by an
external interrupt .
A slot is a field of a data structure for holding a value. A slot normally occupies one
word .
A stack is a data storage structure that uses a ‘first in, last out’ access model.
Adding an item to a stack is called pushing on, and extracting a value is called
popping. A program stack is normally implemented using the Wptr as the stack
pointer. The Areg, Breg and Creg form the evaluation stack .
See evaluation stack .
The state of a process is the data needed for the process to continue execution.
This may include the evaluation stack, Iptr, Wptr, status register and local data.
The status register holds CPU status information which must be saved if an
interrupt occurs but is not saved if the process deschedules. Some status register
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