ST72521 STMICROELECTRONICS [STMicroelectronics], ST72521 Datasheet - Page 149

• Manufacturer Part Number: ST72521
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

CONTROLLER AREA NETWORK (Cont’d)
The figures below show the abort behaviour in the
four possible cases.
Figure 75. Abort and successful transmission
In this case the abort request performed during the
transmission has no effect, as the first transmis-
sion is successful.
Figure 76. Abort and transmission delayed by
busy CAN bus
In this case the NRTX bit is set to abort the trans-
mission after the first attempt. As the first attempt
is successful the READY and BUSY bits are reset
by pCAN and the transmit buffer becomes empty.
An abort is no longer required.
Figure 77. Abort and error during transmission
In this case NRTX (abort request) is set before the
error, thus pCAN resets READY and BUSY after
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
Error
the error (the first attempt). The abort has been
successful and the transmit buffer is empty.
Figure 78. Abort and arbitration lost
In this case the the NRTX bit is set but has no ef-
fect, as the previous transmission attempt failed
due to an arbitration lost. The application waits for
the falling edge of BUSY bit and checks that
READY is still set. This is the case, this means
pCAN has lost the arbitration and LOCK bit can be
safely reset. Abort is immediate and pCAN resets
the READY and BUSY bits.
Timing Considerations
As no interrupt signals that an abort has been suc-
cessful, the application has to wait until the trans-
mit buffer is empty (transmission has been aborted
or transmitted successfully). This time can vary
depending on the case in which the abort is per-
formed (arbitration lost, error or successful trans-
mission). To show the impact of the software work-
around on this timing behaviour
ure 80
case when abort is done by LOCK only) with the
behaviour when NRTX, BUSY and LOCK bits are
used.
Figure 79. Abort by LOCK only - Reference
behaviour
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
compare the reference behaviour (worst
Figure 79
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