ST72521 STMICROELECTRONICS [STMicroelectronics], ST72521 Datasheet - Page 183

• Manufacturer Part Number: ST72521
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V
Figure 100. Connecting Unused I/O Pins
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V
tion. A positive injection is induced by V
on page 163
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see
characteristics, not tested in production.
5. The R
scribed in
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
I
Symbol
INJ(PIN)
I
t
INJ(PIN)
t
t
f(IO)out
r(IO)out
w(IT)in
V
V
R
V
V
C
V
V
I
I
hys
hys
PU
L
S
IH
IH
IO
IL
IL
3)
PU
3)
Figure
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Injected Current on an I/O pin
Total injected current (sum of all I/O
and control pins)
Input leakage current
Static current consumption
Weak pull-up equivalent resistor
I/O pin capacitance
Output high to low level fall time
Output low to high level rise time
External interrupt pulse time
pull-up equivalent resistor is based on a resistive transistor (corresponding I
for more details.
101).
V
DD
10k
Parameter
10k
UNUSED I/O PORT
UNUSED I/O PORT
1)
1)
1)
1)
IN
ST72XXX
6)
>V
ST72XXX
DD
1)
5)
1)
2)
2)
while a negative injection is induced by V
CMOS ports
TTL ports
V
V
Floating input mode
V
C
Between 10% and 90%
IN
DD
DD
SS
IN
L
=50pF
maximum must be respected, otherwise refer to I
=5V
, f
V
V
SS
Figure
OSC
IN
Conditions
V
, and T
DD
Figure 101. Typical I
100). Data based on design simulation and/or technology
V
DD
=5V
A
4)
unless otherwise specified.
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0
2
0.7xV
2.5
Min
50
2
1
Ta=1 40°C
Ta=9 5°C
Ta=2 5°C
Ta=-45 °C
DD
3
PU
3 .5
IN
<V
PU
Vdd (V)
Typ
vs. V
120
0.7
25
25
1
5
4
SS
current characteristics de-
. Refer to
4.5
DD
0.3xV
with V
5
± 25
Max
200
250
0.8
± 4
INJ(PIN)
±1
5.5
Section 12.2.2
DD
ST72521
IN
specifica-
=V
6
183/211
Unit
t
mA
CPU
k
pF
SS
ns
V
A