ST72521 STMICROELECTRONICS [STMicroelectronics], ST72521 Datasheet - Page 186

• Manufacturer Part Number: ST72521
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72521
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Figure 108. Typical Application with RESET pin
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
(I/O ports and control pins) must not exceed I
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
9. Data guaranteed by design, not tested in production.
186/211
t
w(RSTL)out
t
t
Symbol
Required if LVD is disabled
h(RSTL)in
g(RSTL)in
EXTERNAL
V
R
CIRCUIT
V
V
V
I
hys
IO
ON
RESET
OL
IL
IH
USER
IL
max. level specified in
IO
current sunk must always respect the absolute maximum rating specified in
5)
Recommended
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
Input current on RESET pin
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
if LVD is disabled
INJ(RESET)
in
V
DD
Parameter
Section 12.2.2 on page
0.01 F
0.01 F
Section 12.9.1
1)
5)
1)
3)
V
h(RSTL)in
DD
4.7k
4)
VSS
. Otherwise the reset will not be taken into account internally.
2)
can be ignored.
.
163.
DD
V
External pin
Internal reset sources
V
, f
DD
DD
CPU
=5V
R
Conditions
6)7)8)
ON
, and T
Filter
I
IO
=+2mA
A
unless otherwise specified.
GENERATOR
0.85xV
PULSE
Min
2.5
20
20
0
DD
Section 12.2.2
Typ
2.5
0.2
200
30
30
2
0.16xV
and the sum of I
TBD
Max
120
42
42
0.5
INTERNAL
RESET
9)
9)
WATCHDOG
LVD RESET
DD
ST72XXX
Unit
mA
k
ns
V
s
s
s
IO