ST72521 STMICROELECTRONICS [STMicroelectronics], ST72521 Datasheet - Page 208

• Manufacturer Part Number: ST72521
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72521
15.3 FLASH REV “S” AND ROM REV “W”
15.3.1 External clock source with PLL
External clock source is not supported with the
PLL enabled.
15.3.2 LVD Startup behaviour
When the LVD is enabled, the MCU reaches its
authorized operating voltage from a reset state.
However, in some devices, the reset state is re-
leased when VDD is approximately between 0.8V
and 1.5V. As a consequence, the I/Os may toggle
when VDD is within this window.
This may be an issue especially for applications
where the MCU drives power components.
Because Flash write access is impossible within
this window, the Flash memory contents will not be
corrupted.
Figure 125. LVD Startup Behaviour
15.3.3 I/O Port D Configuration
When using an external quartz crystal or ceramic
resonator, the f
cause the device goes into reserved mode control-
led by Port D.
This happens with either one of the following con-
figurations:
– PD[3:1]=010 while CSS and PLL options are
208/211
1.5V
0.8V
5V
V
both disabled and PD4 is toggling
IT+
OSC2
clock may be disturbed be-
Window
LVD RESET
t
– PD[4:1]=1010 while CSS or PLL options are en-
This is detailed in the following table:
As a consequence, for cycle-accurate operations,
these configurations are prohibited in either input
or output mode.
Workaround:
To avoid this occurring, it is recommended to con-
nect one of these pins to GND (PD2 or PD4) or
V
15.4 FLASH Rev “S” DEVICES ONLY
15.4.1 LVD Operation
Depending on the operating conditions, especially
the V
in some cases the LVD may not start. When this
occurs, the MCU may operate outside the guaran-
teed functional area (see datasheet Figure 76)
without being forced into reset state.
In this case, proper use of the watchdog may
make it possible to recover through a watchdog re-
set and allow normal operations to resume.
Consequently, the LVD function is not guaranteed
in the current silicon revision. For complete securi-
ty, an external reset circuit must be added.
CSS PLL PD[3:1]
OFF OFF
DD
abled
ON
x
(PD1 or PD3).
DD
ramp up speed and ambient temperature,
ON
x
010
010
PD4
gling
Tog-
1
Max. 2 clock cy-
cles lost at each
rising or falling
edge of PD4
Max. 1 clock cy-
cle lost out of
every 16
Disturbance
Clock