ST72521 STMICROELECTRONICS [STMicroelectronics], ST72521 Datasheet - Page 192

• Manufacturer Part Number: ST72521
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72521
12.12 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V
Figure 114. R
Figure 116. Typical A/D Converter Application
Notes:
1. Unless otherwise specified, typical data are based on T
lines and are not tested.
2. When V
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k ). Data
based on characterization results, not tested in production.
4. C
pacitance (3pF). A high C
5. This graph shows that depending on the input signal variation (f
decreased to allow the use of a larger serial resistor (R
192/211
Symbol
V
C
t
f
V
R
C
t
STAB
AREF
f
ADC
ADC
AIN
PARASITIC
ADC
AIN
I
AIN
AIN
L
45
40
35
30
25
20
15
10
5
0
DDA
ADC clock frequency
Analog reference voltage
Conversion voltage range
Input leakage current
for analog input
External input impedance
External capacitor on analog input
Variation freq. of analog input signal
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
- No of sample capacitor loading cycles
- No. of Hold conversion cycles
V
0
AIN
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
and V
AIN
max. vs f
SSA
R
10
C
pins are not available on the pinout, the ADC refers to V
AIN
PARASITIC
Parameter
PARASITIC
ADC
(pF)
C
30
AIN
value will downgrade conversion accuracy. To remedy this, f
with C
2)
3)
AINx
2 MHz
1 MHz
AIN
70
=0pF
DD
0.7*V
-40°C T
Other T
f
f
, f
CPU
ADC
4)
AIN)
CPU
A
=8MHz, SPEED=0
=2MHz
=25°C and V
.
DD
Conditions
V
, and T
A
DD
A
Figure 115. Recommended C
V
ranges
V
0.6V
V
0.6V
85°C range
AREF
T
T
1000
AIN
100
0.1
10
1
A
), C
V
unless otherwise specified.
DD
DD
-V
AIN
0.01
SS
2k
can be increased for stabilization time and
=5V. They are given only as design guide-
I
±1 A
L
V
DD
Min
max
0.4
3.8
SSA
0.1
and V
f
AIN
(KHz)
SS
10-Bit A/D
Conversion
Typ
.
0
7.5
12
11
4
1
5)
1)
ADC
AIN
Cain 10 nF
Cain 22 nF
Cain 47 nF
should be reduced.
115
114
Figure
Figure
V
& R
±250
Max
see
5.5
AREF
±1
10
2
3)4)5)
and
ST72XXX
AIN values.
C
12pF
ADC
1/f
Unit
MHz
nA
k
pF
Hz
pF
V
ADC
A
s
5)