ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 25

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

5
The ST18-AU1 has two input serial interfaces (DIN0 and DIN1). The interfaces are multi-
format serial interfaces for inputting audio bitstreams. Supported formats include delayed
(I
input clock, and master/slave mode. They provide the serial to parallel conversion and transfer
the input data to the input buffer for further processing.
Data input interface 0 (DIN0) operates with an input FIFO which regulates the input data flow
transferred to the input buffer. Data input interface 1 (DIN1) operates in a similar way to DIN0
but it does not have an associated input FIFO.
5.1 Input serial interface registers
Each input serial interface has the following set of registers.
DIN0-1CR: Data in control register
On reset, all bits are cleared.
Bit
DINEN
WS
CLK_pol
WS_pol
Delayed
2
15
-
S)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in L/R clock and
14
INPUT SERIAL INTERFACE
-
13
-
Function
Input interface enable
Input word size
Clock polarity
Word size polarity
Delay inserted before first bit of data following transition of WS.
0
1’
Bit1
0
0
1
1
0
1
0
1
0
1
12
-
11
-
input interface disabled
input interface enabled
Bit 0
0
1
0
1
data and WS change on Clk falling edge
data and WS change on Clk rising edge
Left data word = WS low, Right data word = WS high
Left data word = WS high, Right data word = WS low
first bit of data occurs on transition of WS
first bit of data occurs with 1 Clk cycle delay relative to transition of
WS (I
10
-
2
S compatible).
9
-
Input word size
16 bit
18 bit
20 bit
24 bit
8
-
Mas-
ter
7
Justi-
fied
6
layed
De-
5
WS_p
ol
4
CLK_
pol
3
2
WS
ST18-AU1
1
DIN-
EN
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0